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    • 3. 发明授权
    • Electronic timepiece
    • 电子钟表
    • US4223526A
    • 1980-09-23
    • US874052
    • 1978-01-31
    • Teruaki TanakaMasao KaizukaYuichi TakagiMitsuo Aihara
    • Teruaki TanakaMasao KaizukaYuichi TakagiMitsuo Aihara
    • G04F10/00G04G9/00G04G9/12G04G99/00G04B19/30
    • G04G9/126G04G9/0035
    • An electronic timepiece comprises an oscillator, a frequency divider for frequency dividing the output signal of the oscillator to generate 100 Hz output pulse signals, time count circuits having a plurality of counters cascade-connected to count the output pulse signals of the frequency divider, a decoder circuit for decoding the output signal of the time count circuits to generate a display signal and a display device for displaying data corresponding to the output display signal of the decoder circuit, in which a stopwatch display mode and a normal time display mode may be selected by the operation of a switch. The electronic timepiece further includes a control circuit connected between the decoder circuit and display device and adapted to inhibit normal time display data from being supplied to the display device in response to the operation of the switch which sets the electronic timepiece into the stopwatch display mode.
    • 电子钟表包括振荡器,用于对振荡器的输出信号进行分频以产生100Hz输出脉冲信号的分频器,具有串联连接以对分频器的输出脉冲信号进行计数的多个计数器的时间计数电路, 解码器电路,用于解码时间计数电路的输出信号以产生显示信号;以及显示装置,用于显示与解码器电路的输出显示信号相对应的数据,其中可以选择秒表显示模式和正常时间显示模式 通过开关的操作。 电子表还包括连接在解码器电路和显示装置之间的控制电路,并且适于阻止正常时间显示数据被提供给显示装置,以响应将电子表设置为秒表显示模式的开关的操作。
    • 7. 发明授权
    • Negative resistance network
    • 负电阻网络
    • US4015146A
    • 1977-03-29
    • US641385
    • 1975-12-16
    • Mitsuo AiharaShigeho TakadaHisaharu Ogawa
    • Mitsuo AiharaShigeho TakadaHisaharu Ogawa
    • H03B7/06H03H5/12H03H11/52H03K17/687H03K3/53
    • H03H5/12H03H11/52
    • This negative resistance network includes a first predetermined channel insulated gate enhancement type field effect transistor having a drain-source path connected to positive and negative input terminals on which a predetermined input voltage is impressed. The gate potential of the first field effect transistor is controlled by a second insulated gate enhancement type field effect transistor having an opposite channel type to the first field effect transistor, a gate connected to the drain thereof which is connected to the predetermined one of the positive and negative input terminals and a source connected to one pole of a dc power supply having a predetermined voltage, and by a third insulated gate enhancement type field effect transistor having the same channel type as the first field effect transistor, a drain and a gate connected to the drain of the second field effect transistor as well as to the gate of the first field effect transistor and a source connected to the source thereof which is connected to the other input terminal as well as to the other pole of the dc power supply, whereby the first field effect transistor shows a negative resistance characteristic attaining a relatively low current consumption over a relatively wide level range of the input voltage.
    • 该负电阻网络包括第一预定沟道绝缘栅增强型场效应晶体管,漏极源极连接到在其上施加预定输入电压的正输入端和负输入端。 第一场效应晶体管的栅极电位由与第一场效应晶体管相反的沟道类型的第二绝缘栅增强型场效应晶体管控制,连接到其漏极的栅极连接到正的 负极输入端子和连接到具有预定电压的直流电源的一极的源极,以及具有与第一场效应晶体管相同的沟道类型的第三绝缘栅极增强型场效应晶体管,漏极和栅极连接 到第二场效应晶体管的漏极以及连接到其源极的第一场效应晶体管的栅极和连接到另一个输入端子以及直流电源的另一个极的源极, 由此第一场效应晶体管显示相对较宽的电阻消耗相对较低的负电阻特性 输入电压的电平范围。