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1. 发明授权

US06569752B1 Semiconductor element and fabricating method thereof 有权
标题翻译：半导体元件及其制造方法
公开(公告)号：US06569752B1
公开(公告)日：2003-05-27
申请号：US09522820
申请日：2000-03-10
申请人： Soichi Homma , Masahiro Miyata , Hirokazu Ezawa , Junichiro Yoshioka , Hiroaki Inoue , Tsuyoshi Tokuoka
发明人： Soichi Homma , Masahiro Miyata , Hirokazu Ezawa , Junichiro Yoshioka , Hiroaki Inoue , Tsuyoshi Tokuoka
IPC分类号： H01L2144
CPC分类号： H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L2224/02126 , H01L2224/0347 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/05027 , H01L2224/05155 , H01L2224/05164 , H01L2224/05166 , H01L2224/05541 , H01L2224/05558 , H01L2224/05572 , H01L2224/0558 , H01L2224/05639 , H01L2224/1132 , H01L2224/1147 , H01L2224/11901 , H01L2224/11902 , H01L2224/13006 , H01L2224/13023 , H01L2224/13111 , H01L2224/16238 , H01L2224/16507 , H01L2924/00013 , H01L2924/0002 , H01L2924/01004 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/0102 , H01L2924/01022 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01041 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01051 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01092 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/207 , H01L2224/13099 , H01L2924/00014 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/05552
摘要： The present semiconductor element comprises a semiconductor substrate, a wiring pad formed thereon, a layer of barrier metal formed thereon, an intermetallic compound Ag3Sn formed thereon, and a protruded electrode consisting of low-melting metal formed thereon. In addition, a fabricating method of a semiconductor element comprises the steps of forming a wiring pad on a semiconductor substrate, forming a layer of barrier metal thereon, forming a metallic layer containing Ag thereon, forming a layer of low-melting metal containing Sn thereon, and melting the layer of low-melting metal containing Sn to form a protruded electrode and simultaneously to form an intermetallic compound Ag3Sn at an interface between the metallic layer containing Ag and the layer of low-melting metal containing Sn. Thus, with Pb-free solder, a semiconductor element of high reliability can be obtained.
摘要翻译：本半导体元件包括半导体衬底，形成在其上的布线衬垫，形成在其上的阻挡金属层，形成在其上的金属间化合物Ag 3 Sn，以及由其上形成的低熔点金属组成的突出电极。此外，半导体元件的制造方法包括以下步骤：在半导体衬底上形成布线焊盘，在其上形成阻挡金属层，在其上形成含有Ag的金属层，在其上形成含有Sn的低熔点金属层并且熔化含有Sn的低熔点金属层以形成突出电极，同时在包含Ag的金属层和含有Sn的低熔点金属层之间的界面处形成金属间化合物Ag 3 Sn。因此，利用无铅焊料，可以获得高可靠性的半导体元件。

2. 发明授权

US06706422B2 Electroless Ni—B plating liquid, electronic device and method for manufacturing the same 有权
标题翻译：无电镀Ni-B电镀液，电子器件及其制造方法
公开(公告)号：US06706422B2
公开(公告)日：2004-03-16
申请号：US09994834
申请日：2001-11-28
申请人： Hiroaki Inoue , Kenji Nakamura , Moriji Matsumoto , Hirokazu Ezawa , Masahiro Miyata , Manabu Tsujimura
发明人： Hiroaki Inoue , Kenji Nakamura , Moriji Matsumoto , Hirokazu Ezawa , Masahiro Miyata , Manabu Tsujimura
IPC分类号： B32B1504
CPC分类号： C23C18/50 , C23C18/34 , Y10T428/12576 , Y10T428/12896 , Y10T428/12903 , Y10T428/12944 , Y10T428/265
摘要： There is provided an electroless Ni—B plating liquid for forming, a Ni—B alloy film on at least part of the interconnects of an electronic device having an embedded interconnect structure, the electroless Ni—B plating liquid comprising nickel ions, a complexing agent for nickel ions, a reducing agent for nickel ions, and ammonums (NH4+). The electroless Ni—B plating liquid can lower the boron content of the resulting plated film without increasing the plating rate and form a Ni—B alloy film having an FCC crystalline structure.
摘要翻译：提供了一种无电Ni-B电镀液，用于在具有嵌入式互连结构的电子器件的至少一部分互连上形成Ni-B合金膜，包含镍离子的无电Ni-B电镀液，络合剂用于镍离子，镍离子还原剂和氨（NH 4+）。无电镀Ni-B电镀液可以降低所得镀膜的硼含量，而不增加电镀速率，并形成具有FCC晶体结构的Ni-B合金膜。

3. 发明授权

US5500559A Semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5500559A
公开(公告)日：1996-03-19
申请号：US249127
申请日：1994-05-25
申请人： Masahiro Miyata , Hirokazu Ezawa , Naoaki Ogure , Manabu Tsujimura , Takeyuki Ohdaira , Hiroaki Inoue , Yukio Ikeda
发明人： Masahiro Miyata , Hirokazu Ezawa , Naoaki Ogure , Manabu Tsujimura , Takeyuki Ohdaira , Hiroaki Inoue , Yukio Ikeda
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/768 , H01L23/532 , H01L31/06
CPC分类号： H01L21/76873 , H01L21/76843 , H01L21/76858 , H01L21/76877 , H01L23/53242 , H01L23/53247 , H01L2924/0002
摘要： In a semiconductor device and a method for manufacturing the same according to the present invention, for example, an insulating film is deposited on a silicon substrate, and a concave groove is formed in the insulating film in accordance with a predetermined wiring pattern. Titanium and palladium are deposited in sequence on the insulating film to form a titanium film and a palladium film, respectively. A silver film is formed on the palladium film by electroplating, and a groove-shaped silver wiring layer is formed by polishing. The resultant structure is annealed at a temperature of about 700.degree. C., and an intermetallic compound is formed by alloying the titanium film and palladium film with each other. Consequently, a burying type wiring layer whose resistance is lower than that of aluminum, is constituted by the silver wiring layer and intermetallic compound.
摘要翻译：在根据本发明的半导体器件及其制造方法中，例如，在硅衬底上沉积绝缘膜，并且根据预定的布线图案在绝缘膜中形成凹槽。钛和钯依次沉积在绝缘膜上以分别形成钛膜和钯膜。通过电镀在钯膜上形成银膜，通过研磨形成槽状的银布线层。所得结构在约700℃的温度下退火，并通过使钛膜和钯膜彼此合金化形成金属间化合物。因此，电阻低于铝的掩埋型布线层由银布线层和金属间化合物构成。

4. 发明授权

US06936302B2 Electroless Ni-B plating liquid, electronic device and method for manufacturing the same 失效
标题翻译：无电镀Ni-B电镀液，电子器件及其制造方法
公开(公告)号：US06936302B2
公开(公告)日：2005-08-30
申请号：US10765046
申请日：2004-01-28
申请人： Hiroaki Inoue , Kenji Nakamura , Moriji Matsumoto , Hirokazu Ezawa , Masahiro Miyata , Manabu Tsujimura
发明人： Hiroaki Inoue , Kenji Nakamura , Moriji Matsumoto , Hirokazu Ezawa , Masahiro Miyata , Manabu Tsujimura
IPC分类号： C23C18/16 , C23C18/34 , C23C18/50 , H01L21/288 , H01L21/3205 , H01L23/52 , B05D5/12
CPC分类号： C23C18/50 , C23C18/34 , Y10T428/12576 , Y10T428/12896 , Y10T428/12903 , Y10T428/12944 , Y10T428/265
摘要： There is provided an electroless Ni—B plating liquid for forming, a Ni—B alloy film on at least part of the interconnects of an electronic device having an embedded interconnect structure, the electroless Ni—B plating liquid comprising nickel ions, a complexing agent for nickel ions, a reducing agent for nickel ions, and ammonums (NH4+). The electroless Ni—B plating liquid can lower the boron content of the resulting plated film without increasing the plating rate and form a Ni—B alloy film having an FCC crystalline structure.
摘要翻译：提供了一种无电Ni-B电镀液，用于在具有嵌入式互连结构的电子器件的至少一部分互连上形成Ni-B合金膜，包含镍离子的无电Ni-B电镀液，络合剂对于镍离子，用于镍离子的还原剂和氨（NH 4 SO 3 +）。无电镀Ni-B电镀液可以降低所得镀膜的硼含量，而不增加电镀速率，并形成具有FCC晶体结构的Ni-B合金膜。

5. 发明授权

US5705230A Method for filling small holes or covering small recesses in the surface of substrates 失效
标题翻译：填充小孔或覆盖基板表面的小凹槽的方法
公开(公告)号：US5705230A
公开(公告)日：1998-01-06
申请号：US324460
申请日：1994-10-17
申请人： Toru Matanabe , Hirokazu Ezawa , Masahiro Miyata , Yukio Ikeda , Manabu Tsujimura , Hiroaki Inoue , Takeyuki Odaira , Naoaki Ogure
发明人： Toru Matanabe , Hirokazu Ezawa , Masahiro Miyata , Yukio Ikeda , Manabu Tsujimura , Hiroaki Inoue , Takeyuki Odaira , Naoaki Ogure
IPC分类号： C23C18/34 , C23C18/16 , C23C26/00 , C25D5/18 , C25D5/20 , H01L21/48 , H01L21/768 , H05K3/42 , B05D1/18
CPC分类号： C23C18/1608 , C23C18/1612 , C23C18/1651 , C23C18/1666 , C23C18/1831 , H01L21/486 , H01L21/76877 , H05K3/422
摘要： The improved method comprises contacting a substrate 5 at least once by a liquid containing the elements that compose a pure metal or an alloy with which the small holes or recesses 3a in the substrate 5 are to be filled or covered, whereby the liquid wets the inner surfaces of said small holes or recesses 3a while, at the same time, said pure metal or said alloy is deposited on the surface of said substrate 5. The method is capable of filling small holes or covering small recesses in the surface of the substrate 5 with improved efficiency while, at the same time, it improves the heat resistance and materials stability of the part that contains the formed filling or covering layer.
摘要翻译：改进的方法包括使基底5至少一次由含有构成纯金属的元素的液体或与基底5中的小孔或凹槽3a填充或覆盖的合金相接触，由此液体润湿内部所述小孔或凹部3a的表面，同时所述纯金属或所述合金沉积在所述基板5的表面上。该方法能够填充小孔或覆盖基板5的表面中的小凹槽同时提高了包含形成的填充或覆盖层的部件的耐热性和材料稳定性。

6. 发明授权

US5656542A Method for manufacturing wiring in groove 失效
标题翻译：槽内布线方法
公开(公告)号：US5656542A
公开(公告)日：1997-08-12
申请号：US544453
申请日：1995-10-18
申请人： Masahiro Miyata , Hirokazu Ezawa , Naoaki Ogure , Manabu Tsujimura , Takeyuki Ohdaira , Hiroaki Inoue , Yukio Ikeda
发明人： Masahiro Miyata , Hirokazu Ezawa , Naoaki Ogure , Manabu Tsujimura , Takeyuki Ohdaira , Hiroaki Inoue , Yukio Ikeda
IPC分类号： H01L21/768 , H01L23/532 , H01L21/26
CPC分类号： H01L21/76873 , H01L21/76843 , H01L21/76858 , H01L21/76877 , H01L23/53242 , H01L23/53247 , H01L2924/0002
摘要： In a semiconductor device and a method for manufacturing the same according to the present invention, for example, an insulating film is deposited on a silicon substrate, and a concave groove is formed in the insulating film in accordance with a predetermined wiring pattern. Titanium and palladium are deposited in sequence on the insulating film to form a titanium film and a palladium film, respectively. A silver film is formed on the palladium film by electroplating, and a groove-shaped silver wiring layer is formed by polishing. The resultant structure is annealed at a temperature of about 700.degree. C., and an intermetallic compound is formed by alloying the titanium film and palladium film with each other. Consequently, a burying type wiring layer whose resistance is lower than that of aluminum, is constituted by the silver wiring layer and intermetallic compound.
摘要翻译：在根据本发明的半导体器件及其制造方法中，例如，在硅衬底上沉积绝缘膜，并且根据预定的布线图案在绝缘膜中形成凹槽。钛和钯依次沉积在绝缘膜上以分别形成钛膜和钯膜。通过电镀在钯膜上形成银膜，通过研磨形成槽状的银布线层。所得结构在约700℃的温度下退火，并通过使钛膜和钯膜彼此合金化形成金属间化合物。因此，电阻低于铝的掩埋型布线层由银布线层和金属间化合物构成。

7. 发明授权

US06544585B1 Method and apparatus for plating a substrate 有权
标题翻译：电镀基板的方法和装置
公开(公告)号：US06544585B1
公开(公告)日：2003-04-08
申请号：US09145500
申请日：1998-09-02
申请人： Fumio Kuriyama , Akihisa Hongo , Hiroaki Inoue , Tsuyoshi Tokuoka
发明人： Fumio Kuriyama , Akihisa Hongo , Hiroaki Inoue , Tsuyoshi Tokuoka
IPC分类号： B05D512
CPC分类号： H01L21/6715 , H01L21/67144
摘要： A high quality metallic deposit can be produced inside the micro-cavities formed on a surface of a substrate by the present invention. The method involves immersing the substrate in a liquid held in a processing chamber, evacuating the processing chamber so as to remove residual bubbles from the micro-cavities and to degas the liquid within the micro-cavities, and subjecting the liquid to boiling in at least those regions adjacent to the substrate.
摘要翻译：通过本发明，可以在形成在基板的表面上的微孔内产生高质量的金属沉积物。该方法包括将基底浸入保持在处理室中的液体中，抽空处理室以从微孔中除去残余气泡并使微腔内的液体脱气，并至少使液体沸腾那些区域与衬底相邻。

8. 发明授权

US06242624B1 Method for making alkanol-or alkane-sulfone plumbate 失效
标题翻译：制备链烷醇或烷烃 - 砜铅酸铅的方法
公开(公告)号：US06242624B1
公开(公告)日：2001-06-05
申请号：US09568959
申请日：2000-05-11
申请人： Junichiro Yoshioka , Hiroaki Inoue , Kanji Ohno , Akiji Sekiguchi
发明人： Junichiro Yoshioka , Hiroaki Inoue , Kanji Ohno , Akiji Sekiguchi
IPC分类号： C07F724
CPC分类号： C07C309/04 , C07F7/003
摘要： An object of the present invention is to provide a method for obtaining alkanol-sulfonic or alkane-sulfonic plumbates efficiently by improving the solubility of lead oxide compound such as Pb3O4 or PbO2 that are difficult to dissolve in alkanol-sulfonic acid or alkane-sulfonic acid. The method involves reacting difficult-to-dissolve lead oxide compound with a solution of alkanol-sulfonic or alkane-sulfonic acid, wherein a phenol compound is contained in the solution.
摘要翻译：本发明的目的是提供一种通过提高难以溶解在链烷醇 - 磺酸或烷烃 - 磺酸中的Pb 3 O 4或PbO 2等氧化铅化合物的溶解度来有效地获得链烷醇 - 磺酸或烷 - 磺酸铅酸铅的方法该方法包括使难溶溶的氧化铅化合物与链烷醇 - 磺酸或烷烃 - 磺酸的溶液反应，其中溶液中含有酚化合物。

9. 发明授权

US09553604B2 Information processing system, information compression device, information decompression device, information processing method, and program 有权
标题翻译：信息处理系统，信息压缩装置，信息解压装置，信息处理方法和程序
公开(公告)号：US09553604B2
公开(公告)日：2017-01-24
申请号：US13262181
申请日：2010-03-19
申请人： Hiroaki Inoue
发明人： Hiroaki Inoue
IPC分类号： H03M7/30 , G11C7/10 , H04L29/12 , G11C29/00
CPC分类号： H03M7/30 , G11C7/103 , G11C29/003 , H04L29/12311
摘要： In order to improve the compression rate for configuration information including address information and data information when transmitting or storing configuration information which includes addresses and data having differing characteristics, an information compression device is provided with a compressor which receives as input and compresses the configuration information provided with the addresses and data, and a compressed information storage module for storing the configuration information which is compressed, that is, compressed configuration information, as the information to be decompressed for the user, said compressor including an information separating module for separating the configuration information into address information and data information, an address compressor and data compressor which separately compress the separated address information and data information, and a compressed information outputting module for combining the compressed address information and data information and outputting the result as compressed configuration information.
摘要翻译：为了在发送或存储具有不同特征的地址和数据的配置信息的情况下提高包括地址信息和数据信息的配置信息的压缩率，信息压缩装置设置有作为输入接收并压缩提供的配置信息的压缩器具有地址和数据的压缩信息存储模块，以及用于将被压缩的配置信息（即，压缩配置信息）存储为要为用户解压缩的信息的压缩信息存储模块，所述压缩器包括用于分离配置信息的信息分离模块地址信息和数据信息，分离地压缩分离的地址信息和数据信息的地址压缩器和数据压缩器，以及压缩信息输出模块，用于将压缩的地址信息和数据信息并将结果作为压缩配置信息输出。

10. 发明授权

US09164905B2 Semiconductor integrated circuit device, method of controlling semiconductor integrated circuit device, and cache device 有权
标题翻译：半导体集成电路器件，半导体集成电路器件的控制方法及缓存器件
公开(公告)号：US09164905B2
公开(公告)日：2015-10-20
申请号：US13393814
申请日：2010-08-18
申请人： Hiroaki Inoue
发明人： Hiroaki Inoue
IPC分类号： G06F12/00 , G06F12/08
CPC分类号： G06F12/0802 , G06F2212/1028 , Y02D10/13
摘要： There are provided a semiconductor integrated circuit device, a method of controlling a semiconductor integrated circuit device, and a cache device capable of efficiently implementing power saving, wherein the cache device includes a low-voltage operation enabling cache (200), and a small-area cache (300) having a type different from that of the cache (200), the cache (200) and the cache (300) being independently supplied with source voltage; the cache (200) being operable at a voltage lower than the lower limit voltage at which the cache (300) is operable; a cache control unit (400) operating switchable controls between a first mode allowing only the cache (200) to operate, and a second mode allowing the cache (200) or the cache (300) to operate; and the cache (200) in the first mode operating to supply a voltage below the lower limit voltage at which the cache (300) is operable, while interrupting power supply to the cache (300).
摘要翻译：提供了一种半导体集成电路器件，一种半导体集成电路器件的控制方法和能够有效地实现功率节省的高速缓存器件，其中该高速缓存器件包括一个使能高速缓存（200）的低压工作，区域缓存（300）具有与高速缓存（200）不同的类型，高速缓存（200）和高速缓存（300）被独立地提供源电压; 高速缓存（200）可操作在低于高速缓存（300）可操作的下限电压的电压; 高速缓存控制单元（400）在允许仅高速缓存（200）操作的第一模式和允许高速缓存（200）或高速缓存（300）操作的第二模式之间操作可切换控制; 以及在所述第一模式下的所述高速缓存（200）工作以提供低于所述高速缓存（300）可操作的所述下限电压的电压，同时中断向所述高速缓存（300）的电力供应。

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