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    • 5. 发明授权
    • WCDMA transmit architecture
    • WCDMA传输架构
    • US07953377B2
    • 2011-05-31
    • US12119066
    • 2008-05-12
    • Theodoros GeorgantasKonstantinos D. VavelidisSofoklis PlevridisBabis (Charalampos) KapnistisSpyridon Kavadias
    • Theodoros GeorgantasKonstantinos D. VavelidisSofoklis PlevridisBabis (Charalampos) KapnistisSpyridon Kavadias
    • H04B1/02
    • H03G3/3042
    • Wideband-Code Division Multiple Access (W-CDMA) transmit architecture. A baseband digital processing module operates cooperatively with an analog signal processing module to effectuate highly adjustable and highly accurate gain adjustment in accordance with transmitter processing within a communication device. The gain adjustment and/or gain control is partitioned between the digital and analog domains by employing two cooperatively operating digital and analog modules, respectively. Gain adjustment in the analog domain is performed in a relatively more coarse fashion that in the digital domain. If desired, gain adjustment in each of the analog and digital domains is performed across a range of discrete steps. The discrete steps in the analog domain are larger than the discrete steps in the digital domain. Also, the discrete steps in the digital domain may be interposed between two successive discrete steps in the analog domain.
    • 宽带码分多址(W-CDMA)传输架构。 基带数字处理模块与模拟信号处理模块协同工作,以根据通信设备内的发射机处理实现高度可调节和高度准确的增益调整。 增益调节和/或增益控制通过分别使用两个协同操作的数字和模拟模块在数字和模拟域之间进行分区。 模拟域中的增益调整以数字域中相对较粗略的方式执行。 如果需要,在每个模拟和数字域中的增益调整在一系列离散步骤中执行。 模拟域中的离散步长大于数字域中的离散步长。 此外,数字域中的离散步骤可以插入在模拟域中的两个连续离散步骤之间。
    • 6. 发明授权
    • Enhanced polar modulator for transmitter
    • 用于发射机的增强极化调制器
    • US07750750B2
    • 2010-07-06
    • US12115068
    • 2008-05-05
    • Sofoklis PlevridisTheodoros GeorgantasKonstantinos D. Vavelidis
    • Sofoklis PlevridisTheodoros GeorgantasKonstantinos D. Vavelidis
    • H03C3/00
    • H03C5/00H03C3/0925H03C3/0933H03C3/0941H03C3/0958
    • Enhanced polar modulator for transmitter. Within a phase locked loop (PLL), a two point modulation topology is employed in which phase information passes through a limiter (e.g., a +90° or +re/2) in which the phase information dynamic range is divide by a factor (e.g., by 2) and a maximum frequency deviation is also divided by a factor (e.g., by 2). Then, a double balanced up-converter mixer/modulator is implemented to perform gain adjustment (e.g., magnitude and/or amplitude adjustment) and phase changes of 0° and +180° or 0 and +re (e.g., negative gains values may be employed). Phase adjustment in such an architecture is split and provided to both the PLL and to the mixer/modulator of such a polar modulator within a transmitter module such as may be implemented within a communication device (e.g., which may be a wireless communication device). This architecture that includes a PLL with a double balanced up-converter mixer/modulator suppresses even harmonics.
    • 用于发射机的增强极化调制器。 在锁相环(PLL)中,使用两点调制拓扑,其中相位信息通过限制器(例如,+ 90°或+ re / 2),其中相位信息动态范围除以因子 例如,通过2)和最大频率偏差也除以因子(例如,2)。 然后,实现双平衡上变频混频器/调制器来执行增益调整(例如,幅度和/或幅度调整)以及0°和+ 180°或0和+ re的相位变化(例如,负增益值可以是 就业)。 这种架构中的相位调整被分离并提供给发射机模块内的PLL和这种极性调制器的混频器/调制器,例如可以在通信设备(例如,其可以是无线通信设备)内实现。 这种包括具有双平衡上变频混频器/调制器的PLL的架构抑制了偶次谐波。
    • 7. 发明申请
    • Enhanced polar modulator for transmitter
    • 用于发射机的增强极化调制器
    • US20120161892A1
    • 2012-06-28
    • US13412519
    • 2012-03-05
    • Sofoklis PlevridisTheodoros GeorgantasKonstantinos D. Vavelidis
    • Sofoklis PlevridisTheodoros GeorgantasKonstantinos D. Vavelidis
    • H04L27/32
    • H03C5/00H03C3/0925H03C3/0933H03C3/0941H03C3/0958
    • Enhanced polar modulator for transmitter. Within a phase locked loop (PLL), two point modulation topology is employed in which phase information passes through a limiter (e.g., a ±90° or ±π/2), the phase information dynamic range is divided by a factor (e.g., by 2), and a maximum frequency deviation is also divided by a factor (e.g., by 2). Then, a double balanced up-converter mixer/modulator performs gain adjustment (e.g., magnitude and/or amplitude adjustment) and phase changes of 0° and +180° or 0 and +π (e.g., negative gains values may be employed). Phase adjustment in such an architecture is split and provided to both the PLL and to the mixer/modulator of such a polar modulator within a transmitter module such as may be implemented within a communication device (e.g., which may be a wireless communication device). This architecture that includes a PLL with a double balanced up-converter mixer/modulator suppresses even harmonics.
    • 用于发射机的增强极化调制器。 在锁相环(PLL)中,使用两点调制拓扑,其中相位信息通过限幅器(例如±90°或±&pgr / / 2),相位信息动态范围除以因子(例如 ,2),并且最大频率偏差也除以因子(例如,2)。 然后,双平衡升压转换器混频器/调制器执行增益调整(例如,幅度和/或幅度调整)以及0°和+ 180°或0°和+&pgr的相位变化。 (例如,可以采用负增益值)。 这种架构中的相位调整被分离并提供给发射机模块内的PLL和这种极性调制器的混频器/调制器,例如可以在通信设备(例如,其可以是无线通信设备)内实现。 这种包括具有双平衡上变频混频器/调制器的PLL的架构抑制了偶次谐波。