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1. 发明申请

US20050160210A1 Vectored interrupt control within a system having a secure domain and a non-secure domain 有权
标题翻译：具有安全域和非安全域的系统内的向量中断控制
公开(公告)号：US20050160210A1
公开(公告)日：2005-07-21
申请号：US10714562
申请日：2003-11-17
申请人： Simon Watt , Christopher Dornan , Luc Orion , Nicolas Chaussade , Lionel Belnet , Stephane Brochier , David Mansell , Jonathan Callan
发明人： Simon Watt , Christopher Dornan , Luc Orion , Nicolas Chaussade , Lionel Belnet , Stephane Brochier , David Mansell , Jonathan Callan
IPC分类号： G06F9/48 , G06F13/24
CPC分类号： G06F9/4812
摘要： There is provided an apparatus for processing data, said apparatus comprising: a processor operable in a plurality of modes and either a secure domain or a non-secure domain including: at least one secure mode being a mode in said secure domain; and at least one non-secure mode being a mode in said non-secure domain; wherein when said processor is executing a program in a secure mode said program has access to secure data which is not accessible when said processor is operating in a non-secure mode; and a vectored interrupt controller operable to generate an exception handler address for supply to said processor in response to occurrence of an exception condition in accordance with programmable parameters specifying: for each of a plurality of exception conditions, a domain value indicating whether said exception condition should trigger an exception handler in said secure domain or said non-secure domain; for each of said plurality of exception conditions, an exception handler address for use if said exception condition occurs when said processor is operating in that one of said secure domain and said non-secure domain indicated by said domain value; and at least one domain switching exception handler address shared between said plurality of exception conditions for use if said exception condition occurs when said processor is not operating in that one of said secure domain and said non-secure domain indicated by said domain value.
摘要翻译：提供了一种用于处理数据的装置，所述装置包括：可以多种模式操作的处理器，以及安全域或非安全域，包括：至少一种安全模式是所述安全域中的模式; 并且至少一个非安全模式是所述非安全域中的模式; 其中当所述处理器以安全模式执行程序时，所述程序具有访问当所述处理器以非安全模式操作时不可访问的安全数据; 以及向量中断控制器，其可操作以产生异常处理程序地址，以响应于根据可编程参数发生异常情况而向所述处理器供应，所述可编程参数指定：对于多个异常条件中的每一个，指示所述异常条件是否应当在所述安全域或所述非安全域中触发异常处理程序; 对于所述多个异常条件中的每一个，如果当所述处理器在由所述域值指示的所述安全域和所述非安全域中的一个中操作时发生所述异常条件，则使用异常处理程序地址; 以及当所述处理器不在由所述域值指示的所述安全域和所述非安全域中的所述安全域中的任何一个时发生所述异常条件时，在所述多个异常条件之间共享的所述多个异常条件之间共享的至少一个域切换异常处理程序地址。

2. 发明申请

US20050114616A1 Access control in a data processing apparatus 有权
标题翻译：数据处理装置中的访问控制
公开(公告)号：US20050114616A1
公开(公告)日：2005-05-26
申请号：US10933478
申请日：2004-09-03
申请人： Andrew Tune , Peter Aldworth , Simon Watt , Lionel Belnet , David Mansell
发明人： Andrew Tune , Peter Aldworth , Simon Watt , Lionel Belnet , David Mansell
IPC分类号： G06F12/00
CPC分类号： G06F12/1441
摘要： A data processing apparatus and method are provided for controlling access to a slave device, the slave device having an address range associated therewith. The apparatus comprises control storage programmable to define a partition identifying a secure region and a non-secure region in the address range, with the data processing apparatus supporting a plurality of modes of operation including a secure mode, and the control storage being programmable only by software executing in the secure mode. A master device is arranged to issue an access request onto a bus, the access request identifying a sequence of addresses within the address range and including a control signal indicating whether the access request is a secure access request or a non-secure access request. The secure region is only accessible by a secure access request. Further, access control logic is provided which is associated with the slave device, the access control logic being operable to receive the access request from the bus and an indication of the partition from the control storage and, if the access request is a non-secure access request, to prevent access to the secure region.
摘要翻译：提供了一种用于控制对从设备的访问的数据处理设备和方法，该从设备具有与之相关联的地址范围。该装置包括可编程的控制存储器，用于定义识别地址范围中的安全区域和非安全区域的分区，数据处理设备支持包括安全模式的多种操作模式，并且控制存储器仅可由软件在安全模式下执行。主设备被布置为在总线上发出访问请求，该访问请求标识地址范围内的一系列地址，并且包括指示该访问请求是安全访问请求还是非安全访问请求的控制信号。安全区域只能通过安全访问请求访问。此外，提供与从设备相关联的访问控制逻辑，访问控制逻辑可操作以从总线接收访问请求以及来自控制存储器的分区的指示，以及如果访问请求是非安全的访问请求，以防止访问安全区域。

3. 发明申请

US20060101247A1 Apparatus and method for generating constant values 有权
公开(公告)号：US20060101247A1
公开(公告)日：2006-05-11
申请号：US10972769
申请日：2004-10-26
申请人： Jonathan Callan , David Mansell , Christopher Pedley , David Seal
发明人： Jonathan Callan , David Mansell , Christopher Pedley , David Seal
IPC分类号： G06F9/44
CPC分类号： G06F9/30181 , G06F9/30032 , G06F9/30167
摘要： A data processing apparatus and method for generating constant values is provided. The data processing apparatus comprises a data processing unit operable in response to an instruction to perform a data processing operation on one or more data values. Shift logic is operable to selectively apply a shift operation to data to produce one of the data values for the data processing operation. Further, a plurality of registers are provided for storing data. The instruction has a register specifier field for identifying a register and a shift specifier field for specifying a shift to be applied to that register's data in order to produce one of the data values for the data processing operation. The register specifier field is allocatable a distinguished value, and if the register specifier field has that distinguished value, the shift logic is provided with a predetermined value and generates therefrom one of a plurality of constant values dependent on the shift specified by the shift specifier field, the generated constant value then being used as one of the data values for the data processing operation.

4. 发明申请

US20060294319A1 Managing snoop operations in a data processing apparatus 审中-公开
标题翻译：管理数据处理设备中的窥探操作
公开(公告)号：US20060294319A1
公开(公告)日：2006-12-28
申请号：US11454834
申请日：2006-06-19
申请人： David Mansell
发明人： David Mansell
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0842 , Y02D10/13
摘要： A data processing apparatus and method are provided for managing snoop operations. The data processing apparatus comprises a plurality of processing units for executing a number of processes by performing data processing operations requiring access to data in shared memory. Each processing unit has a cache for storing a subset of the data for access by that processing unit, the data processing apparatus employing a snoop-based cache coherency protocol to ensure data access by each processing unit is up-to-date. Each processing unit has a storage element associated therewith identifying snoop control data, whereby when one of the processing units determines that a snoop operation is required having regard to the cache coherency protocol, that processing unit references the snoop control data in its associated storage element in order to determine which of the plurality of processing units are to be subjected to the snoop operation. This can give rise to significant energy savings by avoiding unnecessary cache tag look ups, and can also improve performance.
摘要翻译：提供了一种用于管理窥探操作的数据处理装置和方法。数据处理装置包括用于通过执行需要访问共享存储器中的数据的数据处理操作来执行多个处理的多个处理单元。每个处理单元具有用于存储由该处理单元访问的数据的子集的高速缓存，采用基于窥探的高速缓存一致性协议的数据处理装置来确保每个处理单元的数据访问是最新的。每个处理单元具有与其相关联的存储元件，其识别窥探控制数据，由此当处理单元之一确定在考虑到高速缓存一致性协议时需要窥探操作时，该处理单元将其相关联的存储元件中的侦听控制数据引用以确定多个处理单元中的哪一个将被进行窥探操作。这可以通过避免不必要的缓存标签查找而产生显着的节能，并且还可以提高性能。

5. 发明申请

US20060174155A1 System, method and computer program product for testing software 审中-公开
标题翻译：用于测试软件的系统，方法和计算机程序产品
公开(公告)号：US20060174155A1
公开(公告)日：2006-08-03
申请号：US11049284
申请日：2005-02-03
申请人： David Mansell
发明人： David Mansell
IPC分类号： G06F11/00
CPC分类号： G06F11/3696
摘要： A system, method and computer program product are provided for testing software to be run on a data processing apparatus having a processor for performing data processing operations, a memory for storing data for access by the processor, and at least one temporary storage located between the processor and the memory and operable to temporarily store data to improve speed of access to that data by the processor. The software tested controls the maintenance of data by the at least one temporary storage. The test system comprises a processor simulator for simulating the data processing operations performed by the processor, including issuing an access request when access to a data value is required, the access request causing one or more data access operations to be performed. The test system also includes a temporary storage simulator provided for each temporary storage, and arranged to simulate the operation of that associated temporary storage. Each data access operation of the access request is routed to an appropriate temporary storage simulator, and that temporary storage simulator then determines whether the data required by that data access operation is stored in the temporary storage simulator. If so, the required data is retrieved from the temporary storage simulator rather than from memory. The test system also includes a checker operable to perform a checking operation to check the accuracy of the data retrieved for each data access operation of the access request.
摘要翻译：提供了一种用于测试在具有用于执行数据处理操作的处理器的数据处理装置上运行的软件的系统，方法和计算机程序产品，用于存储由处理器访问的数据的存储器和位于处理器之间的至少一个临时存储器处理器和存储器并且可操作以临时存储数据以提高处理器访问该数据的速度。所测试的软件控制由至少一个临时存储器维护数据。测试系统包括用于模拟由处理器执行的数据处理操作的处理器模拟器，包括当需要访问数据值时发出访问请求，导致执行一个或多个数据访问操作的访问请求。测试系统还包括为每个临时存储器提供的临时存储模拟器，并且被布置成模拟相关联的临时存储器的操作。访问请求的每个数据访问操作被路由到适当的临时存储模拟器，并且该临时存储模拟器然后确定该数据访问操作所需的数据是否存储在临时存储模拟器中。如果是这样，则从临时存储模拟器而不是从存储器检索所需的数据。测试系统还包括检查器，可操作以执行检查操作以检查为访问请求的每个数据访问操作检索的数据的准确性。

6. 发明申请

US20050268106A1 Control of access to a shared resourse in a data processing apparatus 有权
标题翻译：控制数据处理设备中共享资源的访问
公开(公告)号：US20050268106A1
公开(公告)日：2005-12-01
申请号：US11044261
申请日：2005-01-28
申请人： David Mansell , Richard Grisenthwaite , Harry Thomas Fearnhamm , Jeremy Davies
发明人： David Mansell , Richard Grisenthwaite , Harry Thomas Fearnhamm , Jeremy Davies
IPC分类号： G06F1/32 , G06F9/52 , G06F13/10 , G06F13/24 , G06F15/80 , H04K1/00
CPC分类号： G06F13/24 , G06F1/3228
摘要： The present invention provides a data processing apparatus and method of controlling access to a shared resource. The data processing apparatus has a plurality of processors operable to perform respective data processing operations requiring access to the shared resource, and a path is provided interconnecting the plurality of processors. An access control mechanism is operable to control access to the shared resource by the plurality of processors, each processor being operable to enter a power saving mode if access to the shared resource is required but the access control mechanism is preventing access to the shared resource by that processor. Further, each processor is operable, when that processor has access to the shared resource, to issue a notification on the path when access to the shared resource is no longer required by that processor. A processor in the power saving mode is arranged, upon receipt of that notification, to exit the power saving mode and to seek access to the shared resource. This approach has been found to result in significant power savings.
摘要翻译：本发明提供一种控制对共享资源的访问的数据处理装置和方法。数据处理装置具有可操作以执行需要访问共享资源的相应数据处理操作的多个处理器，并且提供互连多个处理器的路径。访问控制机制可操作以控制多个处理器对共享资源的访问，如果需要对共享资源的访问，则每个处理器可操作以进入省电模式，但是访问控制机制阻止对共享资源的访问那个处理器。此外，当处理器具有对共享资源的访问时，每个处理器可操作地在该处理器不再需要对共享资源的访问时在路径上发布通知。处于省电模式的处理器在接收到该通知时被布置为退出省电模式并寻求对共享资源的访问。已经发现这种方法导致显着的功率节省。

7. 发明申请

US20070143581A1 Superscalar data processing apparatus and method 有权
标题翻译：超标量数据处理装置及方法
公开(公告)号：US20070143581A1
公开(公告)日：2007-06-21
申请号：US11312653
申请日：2005-12-21
申请人： David Mansell
发明人： David Mansell
IPC分类号： G06F9/44
CPC分类号： G06F9/3851 , G06F9/3822 , G06F9/3824 , G06F9/3885 , G06F9/3891 , G06F12/0846 , G06F12/0864
摘要： A superscalar data processing apparatus and method are provided for processing operations, the apparatus having a plurality of execution threads and each execution thread being operable to process a sequence of operations including at least one memory access operation. The superscalar data processing apparatus comprises a plurality of execution pipelines for executing the operations, and issue logic for allocating each operation to one of the execution pipelines for execution by that execution pipeline. At least two of the execution pipelines are memory access capable pipelines which can execute memory access operations, and each memory access capable pipeline is associated with a subset of the plurality of execution threads. The issue logic is arranged, for each execution thread, to allocate any memory access operations of that execution thread to an associated memory access capable pipeline. Such a system has been found to provide an effective balance between increasing the efficiency of operation of the superscalar data processing apparatus when employing multiple execution threads whilst also alleviating the need for complex hardware to handle hazard detection.
摘要翻译：提供了一种用于处理操作的超标量数据处理装置和方法，该装置具有多个执行线程，每个执行线程可操作以处理包括至少一个存储器访问操作的一系列操作。超标量数据处理装置包括用于执行操作的多个执行流水线，并发出用于将每个操作分配给一个执行流水线以供该执行流水线执行的逻辑。至少两个执行管线是能够执行存储器访问操作的能够存储器访问的管线，并且每个具有存储器访问能力的流水线与多个执行线程的子集相关联。为每个执行线程安排问题逻辑，以将该执行线程的任何存储器访问操作分配给相关的存储器访问能力管线。已经发现，这种系统在采用多个执行线程时提高超标量数据处理装置的操作效率之间的有效平衡，同时还减少了复杂硬件处理危险检测的需要。

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