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1. 发明授权

US4616212A Two stage weighted capacitor digital to analog converter 失效
标题翻译：两级加权电容数模转换器
公开(公告)号：US4616212A
公开(公告)日：1986-10-07
申请号：US709479
申请日：1985-03-07
申请人： Simon M. Law , Bruce Long
发明人： Simon M. Law , Bruce Long
IPC分类号： H03M1/66 , H03M1/00 , H03M1/74 , H03K13/03
CPC分类号： H03M1/804
摘要： A weighted capacitor digital to analog converter is disclosed which requires two stages but only one conversion step. By the use of an applied reference voltage and two groups of capacitors, the outputs of each group being coupled to an amplifier and feedback capacitor circuit, various capacitors in these groups can be selectively switched from the reference voltage to ground potential in response to input binary digit signals thereby presenting a predetermined amount of voltage to the output amplifiers depending upon the number and particular combination of capacitors switched or non-switched to ground.
摘要翻译：公开了一种加权电容器数模转换器，其需要两个阶段，但仅需要一个转换步骤。通过使用施加的参考电压和两组电容器，每组的输出耦合到放大器和反馈电容器电路，这些组中的各种电容器可以响应于输入二进制选择性地从参考电压切换到地电位从而根据切换或非切换到地的电容器的数量和特定组合向输出放大器呈现预定量的电压。

2. 发明授权

US4667179A Two reference voltage weighted capacitor digital to analog converter 失效
标题翻译：两个参考电压加权电容数模转换器
公开(公告)号：US4667179A
公开(公告)日：1987-05-19
申请号：US709638
申请日：1985-03-07
申请人： Simon M. Law , Thierry L. Watteyne , Dung N. Tran
发明人： Simon M. Law , Thierry L. Watteyne , Dung N. Tran
IPC分类号： H03M1/74 , H03M1/00 , H03M1/68
CPC分类号： H03M1/806
摘要： A weighted capacitor digital to analog converter is disclosed which requires only one stage and one conversion step. By the use of two reference voltages and two groups of capacitors in parallel, various capacitors in these groups can be selectively switched from the reference voltages to ground potential in response to input binary digit signals thereby presenting a predetermined amount of voltage to the output amplifier depending upon the number and particular combination of capacitors switched or non-switched to ground.
摘要翻译：公开了一种加权电容器数模转换器，其仅需要一个阶段和一个转换步骤。通过并联使用两个参考电压和两组电容器，这些组中的各种电容器可以响应于输入二进制数字信号而从参考电压选择性地切换到地电势，从而根据取决于输出放大器的不同而呈现预定量的电压根据电容器的数量和特定组合切换或未切换到地。

3. 发明授权

US6040790A Method of building an adaptive huffman codeword tree 失效
标题翻译：构建自适应huffman码字树的方法
公开(公告)号：US6040790A
公开(公告)日：2000-03-21
申请号：US87389
申请日：1998-05-29
申请人： Simon M. Law
发明人： Simon M. Law
IPC分类号： H03M7/40 , H03M7/42
CPC分类号： H03M7/405 , H03M7/6047
摘要： Many compression algorithms require the compressor to generate trees (tables) for encoding purposes. To generate the optimum tree for a set of Huffman symbols either takes too much time or requires too much hardware. This invention proposes to separate the symbols into groups according to the symbol's occurring frequency. With these groups of symbols available, subsequent code length assignment of these groups can be done without a complete sorting of all the symbols and their parents. During code length assignment, some relocation of individual symbols from one group to another can also be performed to optimize the Huffman table. In most of the cases this technique can achieve a compression ratio within 5% of the optimum Huffman table, while requiring less hardware or software overhead.
摘要翻译：许多压缩算法要求压缩器生成用于编码目的的树（表）。要为一组霍夫曼符号生成最佳树需要太多时间或者需要太多的硬件。本发明提出根据符号发生的频率将符号分成组。使用这些符号组，可以对这些组的后续代码长度分配进行，而无需对所有符号及其父母进行完整排序。在代码长度分配期间，也可以执行单个符号从一个组到另一个组的一些重定位，以优化霍夫曼表。在大多数情况下，这种技术可以在最佳霍夫曼表的5％内实现压缩比，同时要求更少的硬件或软件开销。

4. 发明授权

US5229863A High speed CCITT decompressor 失效
标题翻译：高速CCITT解压缩器
公开(公告)号：US5229863A
公开(公告)日：1993-07-20
申请号：US632781
申请日：1990-12-24
申请人： Jean-Swey Kao , Simon M. Law , Li-Fung Cheung
发明人： Jean-Swey Kao , Simon M. Law , Li-Fung Cheung
IPC分类号： G06T9/00 , H03M7/30 , H03M7/42 , H03M7/46 , H04N1/417
CPC分类号： H03M7/425 , H03M7/46 , H04N1/4175
摘要： A new and improved decoder for decoding CCITT compressed image data. This decoder separates all the incoming codes into short codes and long codes. The short codes are sent to the short channel decoder and the long codes are sent to the long channel decoder. At each decoding cycle either the long channel decoder or the short channel decoder is active. The short channel decoder has a twin set decoder which decodes two short codes in parallel and guarantees two bits of decompressed data per decoding cycle. If the decoding of a first code generates a decompressed data of only one bit, then the decompressed data of a second code will be combined with the first decompressed data and the combination will be sent out. This process guarantees at least two bits of decompressed data per decoding cycle. The long channel decoder decodes the long intermediate codes which always generate at least four bits of decompressed data.
摘要翻译：一种用于解码CCITT压缩图像数据的新型改进解码器。该解码器将所有输入码分成短码和长码。短码被发送到短信道解码器，长码被发送到长信道解码器。在每个解码周期，长信道解码器或短信道解码器都是有效的。短信道解码器具有双集解码器，其并行解码两个短码，并且每个解码周期保证两比特的解压缩数据。如果第一代码的解码产生仅一位的解压缩数据，则第二代码的解压缩数据将与第一解压缩数据组合，并且组合将被发送出去。该过程保证每个解码周期至少两位解压缩的数据。长通道解码器解码总是生成至少四位解压缩数据的长中间码。

5. 发明授权

US5930790A String-match array for substitutional compression 失效
标题翻译：用于替代压缩的字符串匹配数组
公开(公告)号：US5930790A
公开(公告)日：1999-07-27
申请号：US937554
申请日：1997-09-25
申请人： Simon M. Law , Daniel H. Greene , Li-Fung Cheung
发明人： Simon M. Law , Daniel H. Greene , Li-Fung Cheung
IPC分类号： H03M7/40 , G06T9/00 , H03M7/30 , G06F17/30
CPC分类号： G06T9/005 , H03M7/3086 , Y10S707/99936 , Y10S707/99942
摘要： A circuit for implementing a substitutional compressor. Comparators compare a current input pixel against a large number of previous pixels, the "history", stored in a series of shift registers. Each register and associated comparator constitutes a cell. If one or more matches are found the history data is shifted one pixel, the non-matching cells are disabled, and the next input pixel is compared against the contents of the same cells that had the previous matches. The matching is terminated when the longest series of matching pixels is found. The output code is then the length of the matching series of pixels, and the displacement of the first input pixel from the first matching pixel. An encoder generates an initialize signal that resets all of the disabled cells on the same clock cycle on which the output code word is generated. To make the circuit more compact, the cells can be arranged into a square format with one output line for each row and column from the cells to the encoder.
摘要翻译：用于实现替代压缩机的电路。比较器将当前输入像素与大量先前像素“历史”进行比较，存储在一系列移位寄存器中。每个寄存器和相关比较器构成单元。如果找到一个或多个匹配历史数据被移动一个像素，则不匹配的单元被禁用，并且将下一个输入像素与先前匹配的相同单元格的内容进行比较。当找到最长的匹配像素系列时，匹配结束。然后，输出代码是匹配的像素系列的长度，以及第一输入像素与第一匹配像素的位移。编码器产生一个初始化信号，该信号在产生输出代码字的相同时钟周期上复位所有禁用的单元。为了使电路更紧凑，可以将单元格排列成方形格式，每个行和列从单元格到编码器都有一条输出线。

6. 发明授权

US4686396A Minimum delay high speed bus driver 失效
标题翻译：最小延时高速总线驱动
公开(公告)号：US4686396A
公开(公告)日：1987-08-11
申请号：US769520
申请日：1985-08-26
申请人： Simon M. Law , Thien M. Ngo
发明人： Simon M. Law , Thien M. Ngo
IPC分类号： G06F13/40 , G06F3/00 , H03K19/094 , H03K19/096 , H03K19/02 , H03K17/56 , H03K17/687
CPC分类号： H03K19/096 , H03K19/09429
摘要： A minimum delay, high speed, tri-state bus driver is utilized to couple data and control signals to a memory bus with a minimum amount of buffering. Two transistors 24, 26, utilized in a bootstrap configuration, deliver a system clock to the gate terminals of output transistors 28, 30 which are coupled to the memory bus 40. The input data signals and accompanying control signals are applied to these bootstrap transistors 24, 26 via push/pull amplifiers 20, 22 and, depending on the data level of the input data signal, either a logic 1, a logic 0, or a high impedance open circuit is applied to the bus.
摘要翻译：利用最小延迟，高速三态总线驱动器以最小量的缓冲将数据和控制信号耦合到存储器总线。在自举配置中使用的两个晶体管24,26将系统时钟传递到耦合到存储器总线40的输出晶体管28,30的栅极端。输入数据信号和伴随的控制信号被施加到这些自举晶体管24 ，26通过推/拉放大器20,22，并且根据输入数据信号的数据电平，逻辑1，逻辑0或高阻抗开路施加到总线。

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