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    • 1. 发明授权
    • Adaptive digital power control system
    • US07415622B2
    • 2008-08-19
    • US11178671
    • 2005-07-11
    • Simeon MassonChris HearnEdward R. PradoBrian West
    • Simeon MassonChris HearnEdward R. PradoBrian West
    • G06F1/26
    • G06F1/26H02M3/157
    • An adaptive digital power control system is disclosed, which implements a digitally controlled, near real-time algorithm to accommodate multiple loop current mode controls for low voltage, high performance computing system power needs. For example, an adaptive digital power control system that is implemented with an FPGA to generate low voltages for high performance computing systems is disclosed, which includes a current and voltage loop compensation algorithm that enables the adaptive digital power control system to dynamically compensate for high current transients and EMI-related noise. The current and voltage loop compensation algorithm uses a combination of linear predictive coding and Kalman filtering techniques to provide dynamic current and voltage compensation, and implement a feed-forward technique using knowledge of the power system's output parameters to adequately adapt to the system's compensation needs. More specifically, an adaptive digital power control system is disclosed, which includes a power stage for generating a plurality of low voltages, a multiplexer and A/D converter stage for receiving and converting the plurality of low voltages and a plurality of associated currents to a plurality of digital voltage and current signals, a current and voltage compensation algorithm stage for receiving the plurality of digital voltage and current signals and generating a plurality of digital voltage and current compensation control signals using linear predictive coding, Kalman filtering and feed-forward estimation techniques, and a digitally controlled pulse width modulator stage for receiving the plurality of digital voltage and current compensation control signals and controlling the duty cycles of a plurality of transistor switching devices in the power stage. Thus, the adaptive digital power control system can dynamically compensate for high current transients and EMI-related noise generated in low voltage power systems for high performance computing systems.
    • 6. 发明授权
    • System of integrated environmentally hardened architecture for space application
    • 综合环保硬化结构的空间应用系统
    • US07761721B2
    • 2010-07-20
    • US11734482
    • 2007-04-12
    • Jamal HaqueAndrew W. GuyetteEdward R. PradoKeith A. Souders
    • Jamal HaqueAndrew W. GuyetteEdward R. PradoKeith A. Souders
    • G06F1/00G01C23/00G21K1/00G21F1/00
    • G06F11/00
    • An environmentally hardened architecture comprises a hybrid processor, a high speed bus having environmentally-sensitive interfaces, an environmentally hardened bus having environmentally-hardened interfaces, and an environmentally-hardened processor communicatively coupled to an environmentally-sensitive interface of the high speed bus and communicatively coupled to an environmentally-hardened interface of the environmentally hardened bus. The hybrid processor includes an environmentally-hardened processing section and an environmentally-sensitive processing section. At least one environmentally-sensitive interface is configured to pass data to and from the environmentally-sensitive processing section and another environmentally-sensitive interface is configured to pass data to and from the environmentally-hardened processing section of the hybrid processor. An environmentally-hardened interface is configured to pass data to and from the environmentally-hardened processing section of the hybrid processor. The environmentally-hardened processor processes critical applications in the environmentally-hardened processing section of the at least one hybrid processor during an environmental event.
    • 环境坚固的架构包括混合处理器,具有环境敏感界面的高速总线,具有环境硬化接口的环境坚固的总线,以及环境硬化处理器,其通信地耦合到高速总线的环境敏感接口并且可通信地 结合环境坚固的总线的环境坚固的界面。 混合处理器包括环境硬化处理部分和环境敏感处理部分。 至少一个对环境敏感的接口被配置为将数据传送到环境敏感处理部分并且从环境敏感处理部分传出数据,另一个环境敏感接口被配置为将数据传送到混合处理器的环境硬化处理部分和/或从环境硬化处理部分传送数据。 环境坚固的接口被配置为将数据传送到混合处理器的环境硬化处理部分和/或从环境硬化的处理部分传送数据。 环境保护的处理器在环境事件期间处理至少一个混合处理器的环境硬化处理部分中的关键应用。
    • 8. 发明授权
    • System and method for image segmentation
    • 图像分割的系统和方法
    • US07298898B2
    • 2007-11-20
    • US10413378
    • 2003-04-15
    • Jamal HaqueJames D. ParkerMichelle S. WilcoxEdward R. PradoJohn P. Prewitt
    • Jamal HaqueJames D. ParkerMichelle S. WilcoxEdward R. PradoJohn P. Prewitt
    • G06K9/34
    • G06T7/11G06T7/136G06T7/194G06T2200/28
    • An image segmentation apparatus, preferably integrally implemented in a device such as an FPGA, including a buffer memory for storing pixel data, a digital filter in communication with the buffer memory, the digital filter having programmable coefficients, a histogram generating module in communication with the buffer memory that generates a histogram of the pixel data, a statistics generating module in communication with the buffer memory that generates statistics regarding the pixel data, a threshold select module for selecting one of a plurality thresholds and an apply threshold module for applying the selected threshold to data stored in the buffer to generate exceedance data that exceed the selected threshold. In a preferred embodiment, a control module controls each of the buffer, histogram, statistics and threshold modules to control data flow, program filter coefficients and select the appropriate threshold.
    • 一种图像分割装置,优选地整体地实现在诸如FPGA的装置中,包括用于存储像素数据的缓冲存储器,与缓冲存储器通信的数字滤波器,具有可编程系数的数字滤波器,与 生成像素数据的直方图的缓冲存储器,与缓冲存储器通信的统计产生模块,其产生关于像素数据的统计信息;阈值选择模块,用于选择多个阈值中的一个;以及应用阈值模块,用于施加所选择的阈值 存储在缓冲器中的数据以产生超过所选择的阈值的超出数据。 在优选实施例中,控制模块控制缓冲器,直方图,统计和阈值模块中的每一个以控制数据流,程序滤波器系数并选择合适的阈值。