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1. 发明申请

US20170364591A1 DATA PROCESSING CIRCUIT AND DATA PROCESSING METHOD 审中-公开
公开(公告)号：US20170364591A1
公开(公告)日：2017-12-21
申请号：US15408659
申请日：2017-01-18
申请人： Silicon Motion, Inc.
发明人： Jiyun-Wei LIN
IPC分类号： G06F17/30
CPC分类号： G06F16/951
摘要： A data processing circuit includes a condition input circuit and a search engine array. The condition input circuit receives and stores multiple search conditions corresponding to multiple data search tasks. The search engine array receives the search conditions and performs the data search tasks in a parallel manner according to the search conditions. The search engine array includes a storage medium and multiple search engines. The search condition(s) corresponding to one data search task is provided to one search engine and the search engine array accesses a random access memory to load the data stored in the random access memory into the storage medium. The search engines search the data stored in the storage medium according to the corresponding search condition(s) to perform the corresponding data search task, concurrently, and obtain a corresponding search result.

2. 发明申请

US20140380000A1 MEMORY CONTROLLER AND ACCESSING SYSTEM UTILIZING THE SAME 审中-公开
标题翻译：内存控制器和使用该系统的访问系统
公开(公告)号：US20140380000A1
公开(公告)日：2014-12-25
申请号：US14107165
申请日：2013-12-16
申请人： Silicon Motion, Inc.
发明人： Yu-Wei CHYAN , Jiyun-Wei LIN
IPC分类号： G06F3/06
CPC分类号： G06F13/1668
摘要： A memory controller is coupled to a memory device including a first block and a second block and includes a first register module, a first execution unit and a second register module. The first register module includes a plurality of set registers to store a first configuration file and a second configuration file. The first execution unit computes data stored in the first block simultaneously according to the first and the second configuration files to generate a first computation result and a computation operation result. The second register module includes a plurality of result registers to store the first and the second computation results.
摘要翻译：存储器控制器耦合到包括第一块和第二块的存储器件，并且包括第一寄存器模块，第一执行单元和第二寄存器模块。第一寄存器模块包括多个设置寄存器，用于存储第一配置文件和第二配置文件。第一执行单元根据第一和第二配置文件同时计算存储在第一块中的数据，以生成第一计算结果和计算运算结果。第二寄存器模块包括多个结果寄存器来存储第一和第二计算结果。

3. 发明申请

US20180074953A1 MEMORY CONTROLLER AND ACCESSING SYSTEM UTILIZING THE SAME 审中-公开
公开(公告)号：US20180074953A1
公开(公告)日：2018-03-15
申请号：US15816892
申请日：2017-11-17
申请人： Silicon Motion, Inc.
发明人： Yu-Wei CHYAN , Jiyun-Wei LIN
IPC分类号： G06F12/02 , G06F13/16 , G06F3/06 , G06F13/38
CPC分类号： G06F12/0246 , G06F3/06 , G06F3/061 , G06F3/0655 , G06F3/0679 , G06F13/14 , G06F13/16 , G06F13/1694 , G06F13/385 , Y02D10/14 , Y02D10/151
摘要： A memory controller including a first transmittal module, a clock pin, a second transmittal module, a first control module and a second control module is disclosed. The first transmittal module includes a specific pin. The clock pin receives a clock signal. The first transmittal module and the clock pin constitute an embedded multimedia card (eMMC) interface. The second transmittal module and the clock pin constitute a universal flash storage (UFS) interface. The first control module communicates with an external host via the first transmittal module according to the clock signal when a level of the specific pin is at a first level. The second control module communicates with the external host via the second transmittal module according to the clock signal when the level of the specific pin is at a second level. The first level exceeds the second level.

4. 发明申请

US20150134921A1 STORAGE UNIT AND CONTROL SYSTEM 审中-公开
标题翻译：存储单元和控制系统
公开(公告)号：US20150134921A1
公开(公告)日：2015-05-14
申请号：US14304045
申请日：2014-06-13
申请人： Silicon Motion, Inc.
发明人： Jiyun-Wei LIN
IPC分类号： G06F3/06
CPC分类号： G06F3/0658 , G06F3/0611 , G06F3/0659 , G06F3/0679 , G06F2003/0695
摘要： A storage unit coupled to a controller for receiving a first control signal and a second control signal is provided. The storage unit includes a cell array, a first access module and a second access module. The cell array stores data. The first access module accesses the data stored in the cell array according to the first control signal. The second access module processes the data stored in the cell array according to the second control signal to generate a search result and provides the search result to the controller. When the first access module receives the first control signal and the second access module receives the second control signal, the first and second access modules simultaneously operate.
摘要翻译：提供耦合到控制器的存储单元，用于接收第一控制信号和第二控制信号。存储单元包括单元阵列，第一存取模块和第二存取模块。单元格阵列存储数据。第一访问模块根据第一控制信号访问存储在单元阵列中的数据。第二访问模块根据第二控制信号处理存储在单元阵列中的数据，以产生搜索结果，并将搜索结果提供给控制器。当第一访问模块接收到第一控制信号并且第二访问模块接收到第二控制信号时，第一和第二访问模块同时操作。

5. 发明申请

US20190391926A1 APPARATUS AND METHOD AND COMPUTER PROGRAM PRODUCT FOR GENERATING A STORAGE MAPPING TABLE 审中-公开
公开(公告)号：US20190391926A1
公开(公告)日：2019-12-26
申请号：US16149367
申请日：2018-10-02
申请人： Silicon Motion, Inc.
发明人： Jiyun-Wei LIN
IPC分类号： G06F12/10 , G06F13/28
摘要： The invention introduces an apparatus for generating a storage mapping table at least including a direct memory access controller for reading first physical location (PL) information corresponding to a logical location of the storage mapping table; an expanding circuit for obtaining the first PL information and expanding the first PL information into second PL information; and a controller for transmitting the second PL information to a host.

6. 发明申请

US20140304458A1 MEMORY CONTROLLER AND ACCESSING SYSTEM UTILIZING THE SAME 有权
标题翻译：内存控制器和使用该系统的访问系统
公开(公告)号：US20140304458A1
公开(公告)日：2014-10-09
申请号：US14195050
申请日：2014-03-03
申请人： Silicon Motion, Inc.
发明人： Yu-Wei CHYAN , Jiyun-Wei LIN
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F3/06 , G06F3/061 , G06F3/0655 , G06F3/0679 , G06F13/14 , G06F13/16 , G06F13/1694 , G06F13/385 , Y02D10/14 , Y02D10/151
摘要： A memory controller including a first transmittal module, a clock pin, a second transmittal module, a first control module and a second control module is disclosed. The first transmittal module includes a specific pin. The clock pin receives a clock signal. The first transmittal module and the clock pin constitute an embedded multimedia card (eMMC) interface. The second transmittal module and the clock pin constitute a universal flash storage (UFS) interface. The first control module communicates with an external host via the first transmittal module according to the clock signal when a level of the specific pin is at a first level. The second control module communicates with the external host via the second transmittal module according to the clock signal when the level of the specific pin is at a second level. The first level exceeds the second level.
摘要翻译：公开了一种包括第一传输模块，时钟引脚，第二传输模块，第一控制模块和第二控制模块的存储器控制器。第一个传输模块包括一个特定的引脚。时钟引脚接收时钟信号。第一个传输模块和时钟引脚构成嵌入式多媒体卡（eMMC）接口。第二个传输模块和时钟引脚构成通用闪存（UFS）接口。当特定引脚的电平处于第一电平时，第一控制模块通过第一传输模块根据时钟信号与外部主机通信。当特定引脚的电平处于第二电平时，第二控制模块通过第二传输模块根据时钟信号与外部主机通信。第一级超过第二级。

7. 发明申请

US20210049105A1 APPARATUS AND METHOD AND COMPUTER PROGRAM PRODUCT FOR GENERATING A STORAGE MAPPING TABLE 有权
公开(公告)号：US20210049105A1
公开(公告)日：2021-02-18
申请号：US17085068
申请日：2020-10-30
申请人： Silicon Motion, Inc.
发明人： Jiyun-Wei LIN
IPC分类号： G06F12/10 , G06F13/28
摘要： The invention introduces an apparatus for generating a storage mapping table at least including a direct memory access controller for reading first physical location (PL) address corresponding to a logical location of the storage mapping table; an expanding circuit for obtaining the first PL address and expanding the first PL address into second PL address by appending data bits that originally provide different information from a physical address of the flash memory unit to the first PL address; and a controller for transmitting the second PL address without transmitting the first PL address stored in the flash memory unit to a host.

8. 发明申请

US20170277237A1 STORAGE DEVICE AND RESET METHOD THEREOF 审中-公开
公开(公告)号：US20170277237A1
公开(公告)日：2017-09-28
申请号：US15408652
申请日：2017-01-18
申请人： Silicon Motion, Inc.
发明人： Jiyun-Wei LIN
IPC分类号： G06F1/24
CPC分类号： G06F1/24 , G11C16/102 , G11C16/105 , G11C16/20 , G11C16/22 , G11C16/225
摘要： A storage device including a processor, a controller, and a switch is provided. The processor is configured to control a logic circuit. When a main reset signal is enabled, the processor generates a sub-reset signal according to the operation status of the logic circuit. The controller generates a mask signal according to the main reset signal and the sub-reset signal. When the mask signal is enabled, the switch does not transmit the main reset signal to the logic circuit. When the mask signal is not enabled, the switch transmits the main reset signal to the logic circuit to reset the logic circuit.

9. 发明申请

US20160350014A1 Memory Controller and Memory Module 审中-公开
标题翻译：内存控制器和内存模块
公开(公告)号：US20160350014A1
公开(公告)日：2016-12-01
申请号：US15165171
申请日：2016-05-26
申请人： Silicon Motion, Inc.
发明人： Jiyun-Wei LIN
IPC分类号： G06F3/06
CPC分类号： G06F3/0659 , G06F3/061 , G06F3/0656 , G06F3/0679 , G06F11/00 , G06F12/02
摘要： A memory controller coupled between an external device and a memory is provided. The memory controller is coupled to the external device via a second interface and coupled to the memory via a first interface. The memory controller further includes a control logic to control the first interface and the second interface. The control logic sets the second interface to be at a receiving mode to receive a test data from the external device, and sets the first interface to be at a transmitting mode to transmit the test data to the memory. After a predetermined time, the control logic sets the first interface to be at the receiving mode to receive a test result from the memory, and sets the second interface to be at a transmitting mode to transmit the test result to the external device.
摘要翻译：提供耦合在外部设备和存储器之间的存储器控制器。存储器控制器经由第二接口耦合到外部设备，并经由第一接口耦合到存储器。存储器控制器还包括用于控制第一接口和第二接口的控制逻辑。控制逻辑将第二接口设置为接收模式以从外部设备接收测试数据，并将第一接口设置为发送模式，以将测试数据发送到存储器。在预定时间之后，控制逻辑将第一接口设置为接收模式，以从存储器接收测试结果，并将第二接口设置为发送模式，以将测试结果发送到外部设备。

10. 发明申请

US20140380026A1 CONTROL DEVICE AND ACCESS SYSTEM UTILIZING THE SAME 有权
标题翻译：控制装置和使用它的访问系统
公开(公告)号：US20140380026A1
公开(公告)日：2014-12-25
申请号：US14195089
申请日：2014-03-03
申请人： Silicon Motion, Inc.
发明人： Yu-Wei CHYAN , Jiyun-Wei LIN
IPC分类号： G06F9/30
CPC分类号： G06F9/3881 , G06F9/3824 , G06F13/1673 , G06F13/1694
摘要： A control device coupled between a first memory and a second memory and including an execution unit, a first storage unit, a second storage unit, a selection unit and a processing unit is disclosed. The execution unit executes a specific instruction set to access the first and the second memories. The first storage unit is configured to store a first instruction set. The second storage unit is configured to store a second instruction set. The selection unit outputs one of the first and the second instruction sets to serve as the specific instruction set according to a control signal. The processing unit generates the control signal according to an execution state of the execution unit.
摘要翻译：公开了一种耦合在第一存储器和第二存储器之间并包括执行单元，第一存储单元，第二存储单元，选择单元和处理单元的控制设备。执行单元执行特定指令集以访问第一和第二存储器。第一存储单元被配置为存储第一指令集。第二存储单元被配置为存储第二指令集。选择单元根据控制信号输出第一和第二指令集中的一个作为特定指令集。处理单元根据执行单元的执行状态生成控制信号。

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