专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06629175B1 Efficient adapter context switching 失效
标题翻译：高效的适配器上下文切换
公开(公告)号：US06629175B1
公开(公告)日：2003-09-30
申请号：US09550182
申请日：2000-04-14
申请人： Sidney James Manning , James Anthony Pafumi , Robert Paul Stelzer , Timothy Howard White
发明人： Sidney James Manning , James Anthony Pafumi , Robert Paul Stelzer , Timothy Howard White
IPC分类号： G06F1214
CPC分类号： G06F21/84 , G06F9/468 , G06F9/4843 , G06F9/526 , G06F21/6209 , G06F2221/2105 , G06F2221/2147
摘要： A method and system for controlling access to an adapter, such as a graphics adapter, are disclosed. The method includes querying an adapter lock with a first thread. Thereafter, responsive to determining that the lock indicates the first thread does not have access to the adapter, a sequence to obtain access to the adapter is initiated where the sequence includes writing the adapter context corresponding to the first thread. The, sequence may include a ring 3 to ring 0 transition. The method also includes, in response to determining that the lock indicates the first thread has access to the adapter, communicating to the adapter with the first thread without invoking the sequence to obtain access to the adapter. In one embodiment, querying the adapter lock includes writing a first word of the adapter lock using an atomic operation. The method may further include writing a set of command buffers with the first thread and, responsive to determining that the first has access to the adapter, transferring the commands buffers to the adapter. In one embodiment, the sequence to obtain access to the adapter includes the first thread obtaining ownership of a mutex lock prior to updating the adapter context. The sequence to obtain access to the adapter may include updating the adapter lock status to indicate the first thread having access to the adapter.
摘要翻译：公开了一种用于控制对适配器（例如图形适配器）的访问的方法和系统。该方法包括使用第一个线程查询适配器锁。此后，响应于确定锁指示第一线程不能访问适配器，启动获得对适配器的访问的序列，其中序列包括写入与第一线程相对应的适配器上下文。该序列可以包括环3到环0转换。响应于确定锁指示第一线程具有对适配器的访问的响应，该方法还包括在不调用序列的情况下与第一线程通信到适配器以获得对适配器的访问。在一个实施例中，查询适配器锁包括使用原子操作来写入适配器锁的第一个字。该方法还可以包括用第一线程写入一组命令缓冲器，并且响应于确定第一个具有对适配器的访问，将命令缓冲器传送到适配器。在一个实施例中，获得对适配器的访问的序列包括在更新适配器上下文之前获得互斥锁的所有权的第一线程。获得对适配器的访问的顺序可以包括更新适配器锁定状态以指示具有对适配器的访问的第一线程。

2. 发明授权

US07318218B2 System and method for processor thread for software debugging 有权
标题翻译：处理器线程的系统和方法用于软件调试
公开(公告)号：US07318218B2
公开(公告)日：2008-01-08
申请号：US10670834
申请日：2003-09-25
申请人： Maximino Aguilar, Jr. , Sidney James Manning , Mark Richard Nutter , James Michael Stafford
发明人： Maximino Aguilar, Jr. , Sidney James Manning , Mark Richard Nutter , James Michael Stafford
IPC分类号： G06F9/45
CPC分类号： G06F11/366
摘要： A system and method for using a processor thread as a debugger is presented. A computer system boots up and initiates a debugger thread. The debugger thread loads a robust, debugger operating system and executes the debugger operating system. Once the debugger thread is functioning, the debugger thread invokes an operational thread. In turn, the operational thread loads a primary operating system and may run various applications. While the operational thread executes the primary operating system and the applications, the debugger thread monitors the operational thread for proper functionality. When the operational thread crashes or terminates, the debugger thread retrieves operational data from the operational thread and provides the operational data to a software developer for analysis.
摘要翻译：提出了一种使用处理器线程作为调试器的系统和方法。计算机系统启动并启动调试器线程。调试器线程加载一个强大的调试器操作系统，并执行调试器操作系统。一旦调试器线程正常运行，调试器线程调用一个操作线程。反过来，操作线程加载主操作系统并且可以运行各种应用。当操作线程执行主操作系统和应用程序时，调试器线程监视操作线程以获得正确的功能。当操作线程崩溃或终止时，调试器线程从操作线程中检索操作数据，并将操作数据提供给软件开发人员进行分析。

3. 发明授权

US08468532B2 Adjusting CPU time allocated to next thread based on gathered data in heterogeneous processor system having plurality of different instruction set architectures 失效
标题翻译：基于在具有多个不同的指令集架构的异构处理器系统中收集的数据来调整分配给下一个线程的CPU时间
公开(公告)号：US08468532B2
公开(公告)日：2013-06-18
申请号：US11425448
申请日：2006-06-21
申请人： Maximino Aguilar, Jr. , David John Erb , Sidney James Manning , James Michael Stafford
发明人： Maximino Aguilar, Jr. , David John Erb , Sidney James Manning , James Michael Stafford
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F11/3409 , G06F2201/86 , G06F2209/483
摘要： A method that optimizes system performance using performance monitors is presented. The method gathers thread performance data using performance monitors for threads running on either a first ISA processor or a second ISA processor. Multiple first processors and multiple second processors may be included in a single computer system. The first processors and second processors can each access data stored in a common shared memory. The gathered thread performance data is analyzed to determine whether the corresponding thread needs additional CPU time in order to optimize system performance. If additional CPU time is needed, the amount of CPU time that the thread receives is altered (increased) so that the thread receives the additional time when it is scheduled by the scheduler. In one embodiment, the increased CPU time is accomplished by altering a priority value that corresponds to the thread.
摘要翻译：介绍了使用性能监视器优化系统性能的方法。该方法使用在第一ISA处理器或第二ISA处理器上运行的线程的性能监视器收集线程性能数据。多个第一处理器和多个第二处理器可以包括在单个计算机系统中。第一处理器和第二处理器可以各自访问存储在公共共享存储器中的数据。分析收集的线程性能数据，以确定相应的线程是否需要额外的CPU时间，以优化系统性能。如果需要额外的CPU时间，则线程接收的CPU时间量会被更改（增加），以便线程在调度程序调度时收到额外的时间。在一个实施例中，通过改变对应于线程的优先级值来实现增加的CPU时间。

4. 发明授权

US07363544B2 Program debug method and apparatus 有权
标题翻译：程序调试方法和设备
公开(公告)号：US07363544B2
公开(公告)日：2008-04-22
申请号：US10697865
申请日：2003-10-30
申请人： Michael Norman Day , Sidney James Manning
发明人： Michael Norman Day , Sidney James Manning
IPC分类号： G06F11/00 , G06F11/36
CPC分类号： G06F11/3656
摘要： The present invention provides for an apparatus employed to debug a program operating in a supplemental processor when the processor's registers are not readable directly by the debugging operation of a main processor. A program operating in main memory halts due to operational errors. The program code lines save to a cache. In the main processor, a pool of memory is reserved. A copy of the data from the nominally inaccessible supplementary processor registers also transfers to the reserved storage area for processing of the program needing debugging. After the program debugging is complete, a copy of the contents of the memory pool is restored to the memory of the target supplemental processor. A copy of the local store register state and remaining local store data returns to main memory.
摘要翻译：本发明提供一种用于当处理器的寄存器不能通过主处理器的调试操作直接读取时用于调试在辅助处理器中操作的程序的装置。在主存储器中运行的程序由于操作错误而停止。程序代码行保存到缓存。在主处理器中，保留了一个内存池。来自标称不可访问的补充处理器寄存器的数据的副本也传送到预留的存储区域，以便处理需要调试的程序。程序调试完成后，内存池内容的副本将还原到目标补丁处理器的内存中。本地存储寄存器状态和剩余本地存储数据的副本返回到主存储器。

5. 发明申请

US20070300231A1 SYSTEM AND METHOD FOR USING PERFORMANCE MONITOR TO OPTIMIZE SYSTEM PERFORMANCE 失效
标题翻译：使用性能监视器优化系统性能的系统和方法
公开(公告)号：US20070300231A1
公开(公告)日：2007-12-27
申请号：US11425448
申请日：2006-06-21
申请人： Maximino Aguilar , David John Erb , Sidney James Manning , James Michael Stafford
发明人： Maximino Aguilar , David John Erb , Sidney James Manning , James Michael Stafford
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F11/3409 , G06F2201/86 , G06F2209/483
摘要： A system, method, and program product that optimizes system performance using performance monitors is presented. The system gathers thread performance data using performance monitors for threads running on either a first ISA processor or a second ISA processor. Multiple first processors and multiple second processors may be included in a single computer system. The first processors and second processors can each access data stored in a common shared memory. The gathered thread performance data is analyzed to determine whether the corresponding thread needs additional CPU time in order to optimize system performance. If additional CPU time is needed, the amount of CPU time that the thread receives is altered (increased) so that the thread receives the additional time when it is scheduled by the scheduler. In one embodiment, the increased CPU time is accomplished by altering a priority value that corresponds to the thread.
摘要翻译：介绍了使用性能监视器优化系统性能的系统，方法和程序产品。系统使用在第一个ISA处理器或第二个ISA处理器上运行的线程的性能监视器收集线程性能数据。多个第一处理器和多个第二处理器可以包括在单个计算机系统中。第一处理器和第二处理器可以各自访问存储在公共共享存储器中的数据。分析收集的线程性能数据，以确定相应的线程是否需要额外的CPU时间，以优化系统性能。如果需要额外的CPU时间，则线程接收的CPU时间量会被更改（增加），以便线程在调度程序调度时收到额外的时间。在一个实施例中，通过改变对应于线程的优先级值来实现增加的CPU时间。

6. 发明授权

US07669078B2 Method and apparatus for debugging a program on a limited resource processor 有权
标题翻译：用于在有限资源处理器上调试程序的方法和装置
公开(公告)号：US07669078B2
公开(公告)日：2010-02-23
申请号：US11959998
申请日：2007-12-19
申请人： Michael Norman Day , Sidney James Manning
发明人： Michael Norman Day , Sidney James Manning
IPC分类号： G06F11/00 , G06F11/07
CPC分类号： G06F11/3656
摘要： The present invention provides for an apparatus employed to debug a program operating in a supplemental processor when the processor's registers are not readable directly by the debugging operation of a main processor. A program operating in main memory halts due to operational errors. The program code lines save to a cache. In the main processor, a pool of memory is reserved. A copy of the data from the nominally inaccessible supplementary processor registers also transfers to the reserved storage area for processing of the program needing debugging. After the program debugging is complete, a copy of the contents of the memory pool is restored to the memory of the target supplemental processor. A copy of the local store register state and remaining local store data returns to main memory.
摘要翻译：本发明提供一种用于当处理器的寄存器不能通过主处理器的调试操作直接读取时用于调试在辅助处理器中操作的程序的装置。在主存储器中运行的程序由于操作错误而停止。程序代码行保存到缓存。在主处理器中，保留了一个内存池。来自标称不可访问的补充处理器寄存器的数据的副本也传送到预留的存储区域，以便处理需要调试的程序。程序调试完成后，内存池内容的副本将还原到目标补丁处理器的内存中。本地存储寄存器状态和剩余本地存储数据的副本返回到主存储器。

7. 发明申请

US20080163240A1 Using Performance Monitor to Optimize System Performance 审中-公开
标题翻译：使用性能监视器优化系统性能
公开(公告)号：US20080163240A1
公开(公告)日：2008-07-03
申请号：US12049285
申请日：2008-03-15
申请人： Maximino Aguilar , David John Erb , Sidney James Manning , James Michael Stafford
发明人： Maximino Aguilar , David John Erb , Sidney James Manning , James Michael Stafford
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F11/3409 , G06F2201/86 , G06F2209/483
摘要： An approach that optimizes system performance using performance monitors is presented. The system gathers thread performance data using performance monitors for threads running on either a first ISA processor or a second ISA processor. Multiple first processors and multiple second processors may be included in a single computer system. The first processors and second processors can each access data stored in a common shared memory. The gathered thread performance data is analyzed to determine whether the corresponding thread needs additional CPU time in order to optimize system performance. If additional CPU time is needed, the amount of CPU time that the thread receives is altered (increased) so that the thread receives the additional time when it is scheduled by the scheduler. In one embodiment, the increased CPU time is accomplished by altering a priority value that corresponds to the thread.
摘要翻译：介绍了使用性能监视器优化系统性能的方法。系统使用在第一个ISA处理器或第二个ISA处理器上运行的线程的性能监视器收集线程性能数据。多个第一处理器和多个第二处理器可以包括在单个计算机系统中。第一处理器和第二处理器可以各自访问存储在公共共享存储器中的数据。分析收集的线程性能数据，以确定相应的线程是否需要额外的CPU时间，以优化系统性能。如果需要额外的CPU时间，则线程接收的CPU时间量会被更改（增加），以便线程在调度程序调度时收到额外的时间。在一个实施例中，通过改变对应于线程的优先级值来实现增加的CPU时间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式