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1. 发明申请

US20060064653A1 Automatic layout yield improvement tool for replacing vias with redundant vias through novel geotopological layout in post-layout optimization 审中-公开
标题翻译：自动布局生产率改进工具，用于通过后布局优化中的新颖的地理布局来替代具有冗余通孔的过孔
公开(公告)号：US20060064653A1
公开(公告)日：2006-03-23
申请号：US10946686
申请日：2004-09-21
申请人： Shuo Zhang , Yongbo Jia
发明人： Shuo Zhang , Yongbo Jia
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5077
摘要： The present invention provides a new way of improving yield in the physical design stage after detail routing, thereby optimizing integrated circuit (IC) layout designs for manufacturing. Embodied in an automatic layout yield improvement tool, the present invention replaces vias with redundant vias having redundant cut shapes or larger metal overlapping based on a novel geotopological approach to routed layout optimization. The geotopological approach enables the most favorable redundant via candidate to be selected for each modifiable regular via. The tool first checks all potential redundant vias in the order of yield favorableness. The modifiable regular via is then replaced by an ideal redundant via that does not introduce any design rule violations in the geotopological layout. Overcoming the fundamental limitation of geometrical-based solutions and taking advantage of the modification flexibility of the geotopological approach, this invention achieves highly desirable redundant via usage rate and substantial yield improvement.
摘要翻译：本发明提供了一种在细节布线之后在物理设计阶段提高产量的新方法，从而优化用于制造的集成电路（IC）布局设计。本发明在自动布局生产率改进工具中，基于具有冗余切割形状或较大金属重叠的冗余通孔，替代了基于新颖的地理学方法进行布线优化的过孔。地理学方法可以为每个可修改的常规通道选择最有利的冗余通过候选者。该工具首先按照良好的顺序检查所有潜在的冗余通孔。然后，可修改的常规通道将被理想的冗余通道所取代，该通道不会在地理布局中引入任何设计规则违规。克服基于几何的解决方案的基本限制并利用地理学方法的修改灵活性，本发明实现了高度期望的冗余通过使用率和显着的产量提高。

2. 发明申请

US20060288322A1 Incremental geotopological layout for integrated circuit design 失效
公开(公告)号：US20060288322A1
公开(公告)日：2006-12-21
申请号：US11450142
申请日：2006-06-09
申请人： Shuo Zhang , Yongbo Jia
发明人： Shuo Zhang , Yongbo Jia
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Improved integrated circuit (IC) design optimization in the physical design stage after detail routing is provided. A geotopological layout representation is employed, in which some nets are represented by their determined geometrical wiring paths and other nets by their respective wiring topology. In the IC design flow, a routed layout with geometrical wiring paths is transformed into a geotopological layout. All layout modifications are then performed according to the geotopological layout. An embedded design rule checker ensures layout validity. Finally, a new geometrical layout is regenerated accordingly, including all the layout changes for the targeted optimization. This geotopological approach enables an IC designer to modify a routed layout for various optimization targets, while maintaining the exact routing paths of critical nets that are not modifiable. Geotopological layout optimization according to the present invention can be performed on an entire layout, or it can be performed incrementally on one or more sub-layouts of a design.

3. 发明申请

US20060064654A1 Routed layout optimization with geotopological layout encoding for integrated circuit designs 失效
公开(公告)号：US20060064654A1
公开(公告)日：2006-03-23
申请号：US10946918
申请日：2004-09-21
申请人： Shuo Zhang , Yongbo Jia
发明人： Shuo Zhang , Yongbo Jia
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5077
摘要： The present invention provides a new way of optimizing integrated circuit (IC) designs in the physical design stage after detail routing. A key element is a novel hybrid layout representation referred to as the geotopological layout in which some nets are represented by their determined geometrical wiring paths and some by their respective wiring topology at the same time. In the IC design flow, a routed layout with geometrical wiring paths is transformed into a geotopological layout. All layout modifications are then performed according to the geotopological layout. An embedded design rule checker ensures the validity thereof. Finally, a new geometrical layout is regenerated accordingly, including all the layout changes for the targeted optimization. This geotopological approach advantageously enables an IC designer to modify a routed layout for various optimization targets, while advantageously maintaining the exact routing paths of critical nets that are not modifiable.

4. 发明授权

US07526746B2 Incremental geotopological layout for integrated circuit design 失效
标题翻译：集成电路设计的增量式地理布局
公开(公告)号：US07526746B2
公开(公告)日：2009-04-28
申请号：US11450142
申请日：2006-06-09
申请人： Shuo Zhang , Yongbo Jia
发明人： Shuo Zhang , Yongbo Jia
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： Improved integrated circuit (IC) design optimization in the physical design stage after detail routing is provided. A geotopological layout representation is employed, in which some nets are represented by their determined geometrical wiring paths and other nets by their respective wiring topology. In the IC design flow, a routed layout with geometrical wiring paths is transformed into a geotopological layout. All layout modifications are then performed according to the geotopological layout. An embedded design rule checker ensures layout validity. Finally, a new geometrical layout is regenerated accordingly, including all the layout changes for the targeted optimization. This geotopological approach enables an IC designer to modify a routed layout for various optimization targets, while maintaining the exact routing paths of critical nets that are not modifiable. Geotopological layout optimization according to the present invention can be performed on an entire layout, or it can be performed incrementally on one or more sub-layouts of a design.
摘要翻译：提供详细路由后物理设计阶段改进的集成电路（IC）设计优化。采用地理布局表示，其中一些网络由它们确定的几何布线路径和其他网络通过它们各自的布线拓扑来表示。在IC设计流程中，具有几何布线路径的路由布局被转换为地理布局。然后根据地理布局进行所有布局修改。嵌入式设计规则检查器确保布局有效性。最后，相应地重新生成新的几何布局，包括针对目标优化的所有布局更改。这种地理学方法使IC设计人员可以修改各种优化目标的路由布局，同时保持不可修改的关键网络的确切路由路径。根据本发明的地理布局优化可以在整个布局上执行，或者可以在设计的一个或多个子布局上递增地执行。

5. 发明授权

US07131095B2 Routed layout optimization with geotopological layout encoding for integrated circuit designs 失效
标题翻译：路由布局优化与集成电路设计的地理布局编码
公开(公告)号：US07131095B2
公开(公告)日：2006-10-31
申请号：US10946918
申请日：2004-09-21
申请人： Shuo Zhang , Yongbo Jia
发明人： Shuo Zhang , Yongbo Jia
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： The present invention provides a new way of optimizing integrated circuit (IC) designs in the physical design stage after detail routing. A key element is a novel hybrid layout representation referred to as the geotopological layout in which some nets are represented by their determined geometrical wiring paths and some by their respective wiring topology at the same time. In the IC design flow, a routed layout with geometrical wiring paths is transformed into a geotopological layout. All layout modifications are then performed according to the geotopological layout. An embedded design rule checker ensures the validity thereof. Finally, a new geometrical layout is regenerated accordingly, including all the layout changes for the targeted optimization. This geotopological approach advantageously enables an IC designer to modify a routed layout for various optimization targets, while advantageously maintaining the exact routing paths of critical nets that are not modifiable.
摘要翻译：本发明提供了一种在细节路由后物理设计阶段优化集成电路（IC）设计的新方法。一个关键要素是一种新颖的混合布局表示，被称为地理布局，其中一些网由其确定的几何布线路径表示，一些网由其各自的布线拓扑同时表示。在IC设计流程中，具有几何布线路径的路由布局被转换为地理布局。然后根据地理布局进行所有布局修改。嵌入式设计规则检查器确保其有效性。最后，相应地重新生成新的几何布局，包括针对目标优化的所有布局更改。这种地理学方法有利地使得IC设计者可以修改用于各种优化目标的路由布局，同时有利地维护不可修改的关键网络的确切路由路径。

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