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1. 发明授权

US06728526B2 Fractional-N frequency synthesizer with multiple clocks having different timings 失效
标题翻译：具有不同时序的多个时钟的分数N频率合成器
公开(公告)号：US06728526B2
公开(公告)日：2004-04-27
申请号：US09794185
申请日：2001-02-26
申请人： Ryoichi Yamada , Shunsuke Hirano , Yasunori Miyahara , Hisashi Adachi , Hisashi Takahashi , Hiroki Kojima
发明人： Ryoichi Yamada , Shunsuke Hirano , Yasunori Miyahara , Hisashi Adachi , Hisashi Takahashi , Hiroki Kojima
IPC分类号： H04B106
CPC分类号： H03L7/1976
摘要： A frequency synthesizer device comprising a PLL circuit (9) and a frequency-division ratio control circuit (5). The PLL circuit (9) includes a phase comparator (1), a low-pass filter (2), a voltage-controlled oscillator (3), and a variable frequency divider (4). The frequency-division ratio control circuit (5) controls the variable frequency divider (4) such that a frequency division ratio of the variable frequency divider (4) is changed in time and a time average value of the frequency division ratio contains a value below a decimal point. Two different signals of an output signal fdiv of the variable frequency divider (4) and an output fdiv2 obtained via a delay element (10) are used as clocks of an accumulator portion (81) in the frequency-division ratio control circuit (5). The variation in the substrate potential and the variation in the power supply voltage generated by the operation of the frequency-division ratio control circuit (5) can be reduced, and the degradation of C/N of the frequency synthesizer can be suppressed.
摘要翻译：一种频率合成器装置，包括PLL电路（9）和分频比控制电路（5）。 PLL电路（9）包括相位比较器（1），低通滤波器（2），压控振荡器（3）和可变分频器（4）。分频比控制电路（5）控制可变分频器（4），使得可变分频器（4）的分频比在时间上变化，并且分频比的时间平均值包含低于小数点。使用分频比控制电路（5）中的可变分频器（4）的输出信号fdiv和通过延迟元件（10）获得的输出fdiv2的两个不同信号作为累加器部分（81）的时钟，。可以减小由分频比控制电路（5）的操作产生的基板电位的变化和电源电压的变化，并且可以抑制频率合成器的C / N的劣化。

2. 发明申请

US20060055466A1 Modulator and correction method thereof 失效
标题翻译：调制器及其校正方法
公开(公告)号：US20060055466A1
公开(公告)日：2006-03-16
申请号：US10531050
申请日：2004-01-08
申请人： Shunsuke Hirano , Yasunori Miyahara
发明人： Shunsuke Hirano , Yasunori Miyahara
IPC分类号： H03L7/00
CPC分类号： H03C3/0925 , H03C3/0933 , H03C3/0991 , H03L7/1976
摘要： An object of the invention is to provide wideband modulator using a PLL synthesizer which can match the frequency characteristic and prevent degradation in modulation accuracy even in the presence of a variation in the manufacture of circuit components. In a wideband modulator which modulates the division ratio of a frequency divider by using a modulating signal generated by a modulating signal generator and outputs a modulated carrier signal from a VCO, first and second calibration data from a calibration data generator are input via a selector. The amplitude value of an ac component of each modulating signal appearing on the output of a loop filter or the amplitude value of an ac component of each modulating signal demodulated by a demodulator is converted to a digital value by way of an AID converter. The difference between the two is detected by error detection means and a control signal FCR to eliminate the difference is generated by frequency characteristic correction means in order to correct the frequency characteristic of a PLL or a pre-distortion filter.
摘要翻译：本发明的目的是提供一种使用PLL合成器的宽带调制器，其可以匹配频率特性，并且即使在存在电路部件制造的变化的情况下也能防止调制精度的降低。在通过使用由调制信号发生器产生的调制信号来调制分频器的分频比并从VCO输出调制的载波信号的宽带调制器中，经由选择器输入来自校准数据发生器的第一和第二校准数据。出现在环路滤波器的输出上的每个调制信号的交流分量的振幅值或由解调器解调的每个调制信号的交流分量的振幅值通过AID转换器转换成数字值。通过误差检测装置和控制信号FCR检测两者之间的差异，以消除由频率特性校正装置产生的差异，以便校正PLL或预失真滤波器的频率特性。

3. 发明授权

US06871055B2 Direct conversion receiver, mobile radio equipment using the same, and RF signal receiving method 失效
标题翻译：直接转换接收机，移动无线电设备使用相同，以及射频信号接收方式
公开(公告)号：US06871055B2
公开(公告)日：2005-03-22
申请号：US10218658
申请日：2002-08-15
申请人： Shunsuke Hirano , Yasunori Miyahara
发明人： Shunsuke Hirano , Yasunori Miyahara
IPC分类号： H04B1/30 , H04B1/10
CPC分类号： H04B1/30
摘要： In a direction conversion receiver, a quadrature demodulator produces differential signals in a baseband on the basis of a local signal of a frequency synthesizer, with the differential signals being inputted through a first low pass filter, a gain control amplifier and an amplifier to a control unit and a direct current component between the differential signals being extracted in a second low pass filter. In addition, an offset compensating section reduces an offset voltage while the control unit outputs a control signal for the control of the gain control amplifier. The second low pass filter includes a time constant circuit for determining a time constant through the use of resistors and a capacitor, and a time constant changing section. A time constant control unit controls the time constant changing section for a predetermined period of time after the control unit outputs data for the change of a frequency of the local signal so that the time constant of the time constant circuit decreases. This shortens the time needed for the settlement of automatic gain control and prevents the deterioration of demodulation accuracy during a call.
摘要翻译：在方向转换接收机中，正交解调器基于频率合成器的本地信号在基带中产生差分信号，差分信号通过第一低通滤波器，增益控制放大器和放大器输入到控制器单元和在第二低通滤波器中提取的差分信号之间的直流分量。此外，偏移补偿部分减小偏移电压，同时控制单元输出用于控制增益控制放大器的控制信号。第二低通滤波器包括用于通过使用电阻器和电容器来确定时间常数的时间常数电路和时间常数变化部分。时间常数控制单元在控制单元输出用于改变本地信号的频率的数据之后的预定时间段来控制时间常数变化部分，使得时间常数电路的时间常数减小。这缩短了自动增益控制结算所需的时间，并防止了通话过程中解调精度的恶化。

4. 发明授权

US07224237B2 Modulator and correction method thereof 失效
标题翻译：调制器及其校正方法
公开(公告)号：US07224237B2
公开(公告)日：2007-05-29
申请号：US10531050
申请日：2004-01-08
申请人： Shunsuke Hirano , Yasunori Miyahara
发明人： Shunsuke Hirano , Yasunori Miyahara
IPC分类号： H03C3/00 , H03L7/06 , H03L27/20
CPC分类号： H03C3/0925 , H03C3/0933 , H03C3/0991 , H03L7/1976
摘要： The invention concerns a wideband modulator using a PLL synthesizer, which can match the frequency characteristic and prevent degradation in modulation accuracy even in the presence of a variation in the manufacture of circuit components. In a wideband modulator which modulates the division ratio of a frequency divider by using a modulating signal generated by a modulating signal generator and outputs a modulated carrier signal from a VCO, calibration data from a calibration data generator are input via a selector. The amplitude value of an ac component of each modulating signal, either appearing on the output of a loop filter or demodulated by a demodulator, is converted to a digital value by way of an A/D converter. The difference between the two is detected and a control signal FCR to eliminate the difference is generated in order to correct the frequency characteristic of a PLL or a pre-distortion filter.
摘要翻译：本发明涉及使用PLL合成器的宽带调制器，其可以匹配频率特性，并且即使在存在电路部件的制造的变化的情况下也可以防止调制精度的降低。在通过使用由调制信号发生器产生的调制信号来调制分频器的分频比并从VCO输出调制载波信号的宽带调制器中，来自校准数据发生器的校准数据经由选择器输入。出现在环路滤波器的输出端上或由解调器解调的每个调制信号的交流分量的振幅值通过A / D转换器转换成数字值。检测两者之间的差异，并产生消除差异的控制信号FCR，以校正PLL或预失真滤波器的频率特性。

5. 发明授权

US06563387B2 Method and apparatus for synthesizing high-frequency signals for wireless communications 失效
标题翻译：用于合成用于无线通信的高频信号的方法和装置
公开(公告)号：US06563387B2
公开(公告)日：2003-05-13
申请号：US09867348
申请日：2001-05-29
申请人： Shunsuke Hirano , Ryoichi Yamada , Yasunori Miyahara , Yukio Hiraoka , Hisashi Adachi
发明人： Shunsuke Hirano , Ryoichi Yamada , Yasunori Miyahara , Yukio Hiraoka , Hisashi Adachi
IPC分类号： H03L7087
CPC分类号： H03L7/0898 , H03L7/087 , H03L7/099 , H03L7/107 , H03L7/113 , H03L7/199
摘要： A frequency synthesizer is provided with a prescaler 2 and a counter 3, which output a signal having a frequency generated by frequency-dividing an output signal of a VCO 1; a reference frequency divider 5 for frequency-dividing a frequency of a reference signal of a reference signal source 4; a frequency adjusting meas 9 operated in such that a frequency error between the output signal of the counter 5 and the output signal of the reference frequency divider 5 is detected, and in response to this detection result, such a signal is outputted by which either a capacitor value or an inductor value employed in a resonant circuit of the VCO 1 is switched; and also a bias control means for applying an arbitrary voltage V1 to a control voltage terminal of the VCO 1 so as to bring an output signal of a charge pump 7 into a high impedance state when the frequency adjusting means 9 is operated. Since the resonant frequency of the resonant circuit is changed in response to an actual oscillation frequency of the VCO 1, the frequency synthesizer can be phase-locked at a desirable frequency. Also, since the VCO can be manufactured in the IC form, the compact VCO can be made in low cost.
摘要翻译：频率合成器设置有预分频器2和计数器3，该预分频器2和计数器3输出具有通过对VCO 1的输出信号进行分频而产生的频率的信号; 用于对参考信号源4的参考信号的频率进行分频的参考分频器5; 以使得计数器5的输出信号与参考分频器5的输出信号之间的频率误差被检测到的频率调整装置9被执行，并且响应于该检测结果，输出这样一个信号：在VCO 1的谐振电路中使用的电容器值或电感值被切换; 以及偏置控制装置，用于将任意电压V1施加到VCO1的控制电压端，以便当频率调节装置9工作时使电荷泵7的输出信号变为高阻抗状态。由于谐振电路的谐振频率响应于VCO1的实际振荡频率而改变，所以频率合成器可以以期望的频率锁相。此外，由于可以以IC形式制造VCO，所以可以以低成本制造紧凑型VCO。

6. 发明授权

US5640213A Television receiver being driven by either analog broadcasting signals or digital broadcasting signal 失效
标题翻译：电视接收机由模拟广播信号或数字广播信号驱动
公开(公告)号：US5640213A
公开(公告)日：1997-06-17
申请号：US550505
申请日：1995-10-30
申请人： Yasunori Miyahara , Yoshitomo Oumi , Syunichi Anzai , Atsumi Kuze
发明人： Yasunori Miyahara , Yoshitomo Oumi , Syunichi Anzai , Atsumi Kuze
IPC分类号： H04N5/455 , H04N5/46 , H04N1/00
CPC分类号： H04N5/4446 , H04N5/455 , H04N5/4401
摘要： A television receiver having an input section for splitting a reception signal to a first signal and a second signal, first and second mixers for respectively receiving the split reception signals, a local oscillator for outputting first and second local oscillation signals, a 90.degree. phase shifter for providing the first local oscillation signal to another input of the first mixer after phase-shifting by 90.degree., a first output section for directly extracting outputs from the first and the second mixers, and a second output section for outputting a second output obtained by adding a direct output from the first mixer and the output from the second mixer which has passed through another 90.degree. phase shifter.
摘要翻译：一种电视接收机，具有用于将接收信号分割为第一信号的输入部分和第二信号，用于分别接收分离接收信号的第一和第二混频器，用于输出第一和第二本地振荡信号的本地振荡器，90°移相器用于在相移90°之后将第一本地振荡信号提供给第一混频器的另一输入，用于直接提取来自第一和第二混频器的输出的第一输出部分和用于输出由第一和第二混频器输出的第二输出的第二输出部分，添加来自第一混频器的直接输出和已经通过另一个90°移相器的第二混频器的输出。

7. 发明授权

US06259325B1 Single-ended signals to differential signals converter 失效
标题翻译：单端信号到差分信号转换器
公开(公告)号：US06259325B1
公开(公告)日：2001-07-10
申请号：US09448442
申请日：1999-11-24
申请人： Shin'ichiro Ishizuka , Yasunori Miyahara
发明人： Shin'ichiro Ishizuka , Yasunori Miyahara
IPC分类号： H03F304
CPC分类号： H01F17/0006 , H01F2017/0093 , H03D7/1433 , H03D7/1458 , H03D2200/0023 , H03D2200/0084
摘要： The present invention discloses a single-ended signals to differential signals converter. In this invention, a first circuit comprising a transistor outputting single-ended signals and a first spiral inductor connected as an inductor for load use that contributes in determining frequency characteristics of a first circuit to either one of output terminals of higher voltage side and lower voltage side of the transistor, and a second circuit comprising a pair of differential input terminals for inputting differential signals and a second spiral inductor that is magnetically coupled with the first spiral inductor, and both ends thereof are connected to the differential input terminals, respectively, are formed within a monolithic integrated circuit.
摘要翻译：本发明公开了一种单端信号到差分信号转换器。在本发明中，第一电路包括输出单端信号的晶体管和作为用于负载使用的电感器连接的第一螺旋电感器，其有助于确定第一电路的频率特性为高压侧和低电压的输出端中的任一个并且第二电路包括用于输入差分信号的一对差分输入端子和与第一螺旋电感器磁耦合的第二螺旋电感器，并且其两端分别连接到差分输入端子形成在单片集成电路内。

8. 发明授权

US5598221A Broadcasting system discriminating television receiver for differentiating between analog and digital telecast signals 失效
标题翻译：区分电视接收机的广播系统用于区分模拟和数字电视广播信号
公开(公告)号：US5598221A
公开(公告)日：1997-01-28
申请号：US377596
申请日：1995-01-24
申请人： Yasunori Miyahara , Syun-ichi Anzai
发明人： Yasunori Miyahara , Syun-ichi Anzai
IPC分类号： H04N5/46
CPC分类号： H04N5/46
摘要： A broadcasting system discriminating television receiver includes a circuit which applies the FM demodulation discrimination on the output of the FM demodulator in an analog broadcasting, or a circuit which applies a video signal discrimination on a video output which is connected to a circuit which applies an I/Q wave detection on the output of an I/Q detector or a circuit which applies a video signal discrimination on a video output, and means for controlling a signal selector switch (SW) after the channel selector judging from the result of the discriminator.
摘要翻译：鉴别电视接收机的广播系统包括在模拟广播中对FM解调器的输出应用FM解调鉴别的电路，或者在连接到应用了I的电路的视频输出上应用视频信号鉴别的电路对I / Q检测器或对视频输出端施加视频信号鉴别的电路的输出进行/ Q波检测，以及用于在频道选择器根据鉴别器的结果进行判断之后控制信号选择器开关（SW）的装置。

9. 发明授权

US5774195A Broadcasting system discriminating television receiver for differentiating between analog and digital telecast signals 失效
标题翻译：区分电视接收机的广播系统用于区分模拟和数字电视广播信号
公开(公告)号：US5774195A
公开(公告)日：1998-06-30
申请号：US967503
申请日：1997-11-12
申请人： Yasunori Miyahara , Syun-ichi Anzai
发明人： Yasunori Miyahara , Syun-ichi Anzai
IPC分类号： H04N5/46 , H04N1/00
CPC分类号： H04N5/46 , H04N21/42607 , H04N21/44209
摘要： A broadcasting system discriminating television receiver including a circuit for evaluating the output of an FM demodulator, a circuit for evaluating the output of an I/Q wave detector, and a controller for controlling a switch based on the results of each evaluation. The switch is used primarily to determine whether the output of the receiver is analog or digital.
摘要翻译：鉴别电视接收机的广播系统，包括用于评估FM解调器的输出的电路，用于评估I / Q波检测器的输出的电路，以及用于根据每次评估的结果来控制开关的控制器。该开关主要用于确定接收器的输出是模拟还是数字。

10. 发明授权

US4724337A Automatic gain control detection circuit 失效
标题翻译：自动增益控制检测电路
公开(公告)号：US4724337A
公开(公告)日：1988-02-09
申请号：US844608
申请日：1986-03-27
申请人： Jyoji Maeda , Kazuo Hasegawa , Yasunori Miyahara
发明人： Jyoji Maeda , Kazuo Hasegawa , Yasunori Miyahara
IPC分类号： H03G3/30 , H03G1/04 , H03G3/20 , H03K5/00 , H03F3/45
CPC分类号： H03G3/3005 , H03G1/04
摘要： An automatic gain control (AGC) detection circuit. The AGC detection circuit includes; a current source, first to fourth transistors whose emitters are connected in common to the current source, a reference voltage source for supplying the bases of the first and the second transistors with a reference voltage, input terminal means connected to the bases of the third and the fourth transistors for receiving an input signal, a power supply source for supplying the first to fourth transistors with a power supply voltage, first collector load means connected between the power supply source and a node connecting the collectors of the first and second transistors in common, second collector load means connected between the power supply source and another node connecting the collectors of the third and fourth transistors in common, and an output terminal means connected between the nodes for taking out an automatic gain control detection output.
摘要翻译：自动增益控制（AGC）检测电路。 AGC检测电路包括：电流源，其发射极共同连接到电流源的第一至第四晶体管，用于向第一和第二晶体管的基极提供参考电压的参考电压源，连接到第三和第三晶体管的基极的输入端子装置，用于接收输入信号的第四晶体管，用于向第一至第四晶体管提供电源电压的电源;第一集电极负载装置，连接在电源和连接第一和第二晶体管的集电极之间的节点连接在电源和共同连接第三和第四晶体管的集电极的另一节点之间的第二集电极负载装置，以及连接在节点之间用于取出自动增益控制检测输出的输出端装置。

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