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1. 发明授权

US07675175B2 Semiconductor device having isolated pockets of insulation in conductive seal ring 有权
标题翻译：半导体器件在导电密封环中具有隔离的绝缘袋
公开(公告)号：US07675175B2
公开(公告)日：2010-03-09
申请号：US11150107
申请日：2005-06-13
申请人： Shunichi Tokitoh , Seiichi Kondou , Bo Un Yoon
发明人： Shunichi Tokitoh , Seiichi Kondou , Bo Un Yoon
IPC分类号： H01L23/48
CPC分类号： H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device with a damascene wiring structure which can prevent short-circuits between a seal ring and a wiring line or electrode pad. An upper layer barrier layer made from a conductive barrier material film is formed on an interlayer insulating film groove sidewall of the semiconductor device. Embedded in the groove is an upper layer seal ring wiring line with thickness of approximately 10 micrometers for instance, in which a plurality of isolated pockets of insulators are disbursed. These isolated pockets of insulators are formed using the interlayer insulating film which forms the damascene wiring line. Additionally, a first upper layer groove wiring line and a second upper layer groove wiring line are formed in an element forming region, and an upper layer barrier layer is formed on the outside perimeter. The upper layer seal ring wiring line and both upper layer wiring lines all have damascene wiring structures.
摘要翻译：具有镶嵌线结构的半导体器件，其可以防止密封环与布线或电极垫之间的短路。在半导体器件的层间绝缘膜槽侧壁上形成由导电阻挡材料膜制成的上层阻挡层。嵌入凹槽中的是上层密封环布线，例如厚度约为10微米，其中多个隔离的绝缘体袋被分配。使用形成镶嵌线的层间绝缘膜形成这些隔离的绝缘体袋。此外，在元件形成区域中形成第一上层槽布线和第二上层槽布线，并且在外周上形成上层阻挡层。上层密封环布线和两层上层布线都具有镶嵌布线结构。

2. 发明申请

US20060001165A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060001165A1
公开(公告)日：2006-01-05
申请号：US11150107
申请日：2005-06-13
申请人： Shunichi Tokitoh , Seiichi Kondou , Bo Un Yoon
发明人： Shunichi Tokitoh , Seiichi Kondou , Bo Un Yoon
IPC分类号： H01L23/48
CPC分类号： H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device with a damascene wiring structure which can prevent short-circuits between a seal ring and a wiring line or electrode pad. The upper layer barrier layer made from a conductive barrier material film is formed on the interlayer insulating film groove sidewall of the semiconductor device, an upper layer seal ring wiring line with the thickness of approximately 10 micrometers for instance made from a wiring material film is embedded in a groove, and a plurality of isolated pockets of insulators are formed to be disbursed in the upper layer seal ring wiring line. These isolated pockets of insulators formed using the interlayer insulating film which forms the aforementioned damascene wiring line. Furthermore, a first upper layer groove wiring line and a second upper layer groove wiring line are formed in the element forming region, and an upper layer barrier layer is formed on the outside perimeter. The upper layer seal ring wiring line and both upper layer wiring lines all have (dual) damascene wiring structures.
摘要翻译：具有镶嵌线结构的半导体器件，其可以防止密封环与布线或电极垫之间的短路。由导电阻挡材料膜制成的上层阻挡层形成在半导体器件的层间绝缘膜槽侧壁上，例如由布线材料膜制成的厚度约为10微米的上层密封环布线并且在上层密封环布线中形成多个隔离的绝缘体袋。使用形成上述镶嵌线的层间绝缘膜形成这些隔离的绝缘体袋。此外，在元件形成区域中形成第一上层槽布线和第二上层槽布线，并且在外周上形成上层阻挡层。上层密封环布线和两层上层布线都具有（双）镶嵌布线结构。

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