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1. 发明授权

US4929984A Resonant tunnelling barrier structure device 失效
标题翻译：谐振隧道势垒结构装置
公开(公告)号：US4929984A
公开(公告)日：1990-05-29
申请号：US265814
申请日：1988-11-01
申请人： Shunichi Muto , Tsuguo Inata , Atsushi Takeuchi , Yoshihiro Sugiyama
发明人： Shunichi Muto , Tsuguo Inata , Atsushi Takeuchi , Yoshihiro Sugiyama
IPC分类号： H01L29/201 , H01L21/20 , H01L29/205 , H01L29/88
CPC分类号： B82Y10/00 , H01L29/205 , H01L29/882
摘要： A resonant tunnelling barrier (RTB) structure device (e.g., diode), having a large peak-to-valley current density (Jp/Jv) ratio, includes an InP substrate and a RTB structure structure. The RTB structure is formed by a first doped layer of InP or In.sub.0.53 GA.sub.0.47 As, a first barrier layer of Al.sub.x Ga.sub.1-x As.sub.y Sb.sub.1-y (0.ltoreq.x.ltoreq.1, y=0.51+0.05x), a well layer of InP or In.sub.z Ga.sub.1-z As (0.52.ltoreq.z.ltoreq.0.54), a second barrier layer of the AlGaAsSb, and a second doped layer of InP or In.sub.z Ga.sub.1-z As. The layers of the RTB structure are lattice-matched to InP.

2. 发明授权

US4825264A Resonant tunneling semiconductor device 失效
标题翻译：谐振隧道半导体器件
公开(公告)号：US4825264A
公开(公告)日：1989-04-25
申请号：US81340
申请日：1987-08-04
申请人： Tsuguo Inata , Shunichi Muto , Toshio Fujii
发明人： Tsuguo Inata , Shunichi Muto , Toshio Fujii
IPC分类号： H01L29/88 , H01L29/201 , H01L29/205 , H01L29/737 , H01L29/76 , H01L29/86 , H01L27/12 , H01L29/161 , H01L29/72 , H01L45/00
CPC分类号： B82Y10/00 , H01L29/205 , H01L29/7376 , H01L29/7606 , H01L29/882
摘要： A resonant tunneling semiconductor device having a large peak-to-valley current density J.sub.p /J.sub.v ratio comprises an InP substrate, a first contact compound semiconductor lattice-matched to Inp, a first barrier layer of (In.sub.0.52 Al.sub.0.48 As).sub.z (In.sub.0.53 Ga.sub.0.47 As).sub.1-z, (0
摘要翻译：具有大的峰谷电流密度Jp / Jv比的谐振隧穿半导体器件包括InP衬底，与Inp晶格匹配的第一接触化合物半导体，（In0.52Al0.48As）z（In0.52Al0.48As）z的第一势垒层（0.38 Ga 0.47 As）1-z，（0 y = 0.46），（In 0.52 Al 0.48 As ）z-（In 0.53 Ga 0.47 As）1-z，（0

3. 发明授权

US5266814A Optically activated resonant-tunneling transistor 失效
标题翻译：光电激活谐振隧道晶体管
公开(公告)号：US5266814A
公开(公告)日：1993-11-30
申请号：US757185
申请日：1991-09-10
申请人： Tsuguo Inata , Shunichi Muto
发明人： Tsuguo Inata , Shunichi Muto
IPC分类号： H01L29/68 , H01L29/20 , H01L31/0352 , H01L31/11 , H01L27/14 , H01L31/00
CPC分类号： B82Y20/00 , H01L31/035236 , H01L31/11
摘要： A resonant-tunneling transistor comprises a first semiconductor layer acting as a collector, a second semiconductor layer provided on the first semiconductor layer and forming a potential barrier of electrons in the conduction band, a third semiconductor layer provided on the second semiconductor layer and forming a quantum well of electrons in the conduction band, a fourth semiconductor layer provided on the third semiconductor layer and forming a quantum well of holes in the valence band, the fourth semiconductor layer simultaneously forming a potential barrier of electrons in the conduction band, a fifth semiconductor layer provided on the fourth semiconductor layer acting as an emitter, a first electrode provided in contact with the first semiconductor layer for recovering electrons therefrom, a second electrode provided in contact with the fifth semiconductor layer for injecting electrons thereinto, and an optical passage for introducing an optical beam to the first semiconductor layer.
摘要翻译：谐振隧穿晶体管包括用作集电极的第一半导体层，设置在第一半导体层上并在导带中形成电子势垒的第二半导体层，设置在第二半导体层上的第三半导体层，在导带中的电子的量子阱，设置在第三半导体层上并形成价带中的空穴的量子阱的第四半导体层，第四半导体层同时在导带中形成电子的势垒，第五半导体设置在用作发射极的第四半导体层上的第一电极，与第一半导体层接触以用于从其中回收电子的第一电极，与第五半导体层接触以用于向其中注入电子的第二电极，以及用于引入电子的光学通道到第一半导体的光束层。

4. 发明授权

US5216261A Non-linear optical device having an improved rate for recovery 失效
标题翻译：具有提高恢复率的非线性光学设备
公开(公告)号：US5216261A
公开(公告)日：1993-06-01
申请号：US810090
申请日：1991-12-19
申请人： Tsuguo Inata , Shunichi Muto
发明人： Tsuguo Inata , Shunichi Muto
IPC分类号： G02F1/015 , G02F1/017 , G02F1/21 , G02F1/35
CPC分类号： B82Y20/00 , G02F1/01716 , G02F1/218
摘要： A non-linear optical device having the TBQ structure comprises an active layer forming a quantum well for interacting with an incident optical beam, an electron removal layer provided adjacent to the active layer at a first side thereof with a first barrier layer intervening therebetween for removing the electrons from the active layer; and a hole removal layer provided adjacent to the active layer at a second, opposite side of the active layer with a second barrier layer intervening therebetween for removing the holes from the active layer; wherein the first and second barrier layers have respective thicknesses determined such that the probability of tunneling of the electrons through the first barrier layer and the probability of tunneling of the holes through the second barrier layer are substantially equal with each other.

5. 发明授权

US4593301A High electron mobility semiconductor device employing selectively doped heterojunction and dual, undoped spacer layers 失效
标题翻译：采用选择性掺杂的异质结和双重未掺杂间隔层的高电子迁移率半导体器件
公开(公告)号：US4593301A
公开(公告)日：1986-06-03
申请号：US707290
申请日：1985-03-01
申请人： Tsuguo Inata , Shigehiko Sasa
发明人： Tsuguo Inata , Shigehiko Sasa
IPC分类号： H01L29/812 , H01L21/338 , H01L29/00 , H01L29/205 , H01L29/778 , H01L29/80
CPC分类号： H01L29/7787
摘要： In order to make IC comprising high electron mobility semiconductor device, it is necessary to make the carrier in channel layer not to loose its high mobility by thermal treatment in the IC fabrication process. It has been found that the mobility of two dimensional electron gas (2DEG) is lost by scattering of ionized impurity diffused from doped layer into spacer layer which separates the 2DEG in channel layer from the doped layer. So another spacer (second spacer) is inserted between the spacer (first spacer) and the doped layer to prevent the diffusion of impurity. Proposed multilayered structure is as follows. A channel layer made of i-GaAs is formed on a high resistivity GaAs substrate. Upon which a first spacer layer (prior art) of undoped Al.sub.x Ga.sub.1-x As is formed, over which the second spacer layer of i-GaAs is formed, then over which the doped layer of n-Al.sub.x Ga.sub.1-x As is formed. The thickness of the second spacer layer is approximately 20 .ANG., and that of the first spacer is approximately 40 .ANG.. Applying such structure to the high electron mobility transistor, it could bear the heat treatment of 750.degree. C. 10 min. and more that 950.degree. C. 10 sec. annealing.
摘要翻译：为了制造包含高电子迁移率半导体器件的IC，需要通过IC制造工艺中的热处理使沟道层中的载体不会失去其高迁移率。已经发现，通过从掺杂层扩散的离子化杂质的散射损失了二维电子气（2DEG）的迁移率到将沟道层中的2DEG与掺杂层分离的间隔层。因此，在间隔物（第一间隔物）和掺杂层之间插入另外的间隔物（第二间隔物），以防止杂质的扩散。拟议的多层结构如下。在高电阻GaAs衬底上形成由i-GaAs制成的沟道层。在其上形成未掺杂的Al x Ga 1-x As的第一间隔层（现有技术），在其上形成i-GaAs的第二间隔层，然后在其上形成n-Al x Ga 1-x As的掺杂层。第二间隔层的厚度约为20，第一间隔物的厚度约为40。将这种结构应用于高电子迁移率晶体管，可以承受750℃的热处理10分钟。更多的是950℃10秒。退火。

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