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1. 发明申请

US20050062515A1 Pulse output circuit, shift register and electronic equipment 有权
标题翻译：脉冲输出电路，移位寄存器和电子设备
公开(公告)号：US20050062515A1
公开(公告)日：2005-03-24
申请号：US10958568
申请日：2004-10-06
申请人： Shou Nagao , Yoshifumi Tanada , Yutaka Shionoiri , Hiroyuki Miyake
发明人： Shou Nagao , Yoshifumi Tanada , Yutaka Shionoiri , Hiroyuki Miyake
IPC分类号： G02F1/1345 , G02F1/133 , G02F1/1368 , G06F1/04 , G09G3/20 , G09G3/36 , G11C19/00 , G11C19/28 , H01L51/50 , H03K3/013 , H03K3/353 , H03K17/00 , H03K17/693 , H03K19/0175 , H03L5/00 , H05B33/14
CPC分类号： G11C19/28 , G09G3/3688 , G09G2310/0275 , G11C19/00
摘要： A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs 101 and 104 to turn ON the TFTs and a potential of a node α is raised. When the potential of the node α reaches (VDD−VthN), the node α becomes in a floating state. Accordingly, a TFT 105 is turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential of a gate electrode of the TFT 105 is further raised due to an operation of a capacitance means 107 as the potential of the output node is raised, so that the potential of the gate electrode of the TFT 105 becomes higher than (VDD+VthN). Thus, the potential of the output node is raised to VDD without causing a voltage drop due to a threshold voltage of the TFT 105. An output at the subsequent stage is then inputted to a TFT 103 to turn the TFT 103 ON, while the potential of the node α of TFTs 102 and 106 is dropped to turn the TFT 105 OFF. As a result, the potential of the output node becomes Low level.
摘要翻译：一种显示装置的驱动电路，其包括单导电类型的TFT并输出具有正常振幅的输出信号。一个脉冲被输入到TFT101和104，使TFT导通，并且提高节点α的电位。当节点α的电位达到（VDD-VthN）时，节点α变为浮动状态。因此，随着时钟信号变为高电平，TFT 105导通，输出节点的电位升高。另一方面，随着输出节点的电位升高，由于电容装置107的操作，TFT 105的栅电极的电位进一步上升，使得TFT 105的栅电极的电位变为高于（VDD + VthN）。因此，输出节点的电位升高到VDD，而不会由于TFT 105的阈值电压引起电压降。然后，后级的输出被输入到TFT103，使TFT103导通，同时电位的TFT102和106的节点α的下降以使TFT 105关闭。结果，输出节点的电位变为低电平。

2. 发明申请

US20060280279A1 Pulse Output Circuit, Shift Register and Electronic Equipment 审中-公开
标题翻译：脉冲输出电路，移位寄存器和电子设备
公开(公告)号：US20060280279A1
公开(公告)日：2006-12-14
申请号：US11467022
申请日：2006-08-24
申请人： Shou Nagao , Yoshifumi Tanada , Yutaka Shionoiri , Hiroyuki Miyake
发明人： Shou Nagao , Yoshifumi Tanada , Yutaka Shionoiri , Hiroyuki Miyake
IPC分类号： G11C19/00
CPC分类号： G11C19/28 , G09G3/3688 , G09G2310/0275 , G11C19/00
摘要： A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs 101 and 104 to turn ON the TFTs and a potential of a node α is raised. When the potential of the node α reaches (VDD−VthN), the node α becomes in a floating state. Accordingly, a TFT 105 is turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential of a gate electrode of the TFT 105 is further raised due to an operation of a capacitance means 107 as the potential of the output node is raised, so that the potential of the gate electrode of the TFT 105 becomes higher than (VDD+VthN). Thus, the potential of the output node is raised to VDD without causing a voltage drop due to a threshold voltage of the TFT 105. An output at the subsequent stage is then inputted to a TFT 103 to turn the TFT 103 ON, while the potential of the node α of TFTs 102 and 106 is dropped to turn the TFT 105 OFF. As a result, the potential of the output node becomes Low level.
摘要翻译：一种显示装置的驱动电路，其包括单导电类型的TFT并输出具有正常振幅的输出信号。一个脉冲被输入到TFT101和104，使TFT导通，并且提高节点α的电位。当节点α的电位达到（VDD-VthN）时，节点α变为浮动状态。因此，随着时钟信号变为高电平，TFT 105导通，输出节点的电位升高。另一方面，随着输出节点的电位升高，由于电容装置107的操作，TFT 105的栅电极的电位进一步上升，使得TFT 105的栅电极的电位变为高于（VDD + VthN）。因此，输出节点的电位升高到VDD，而不会由于TFT 105的阈值电压引起电压降。然后，随后阶段的输出被输入到TFT 103以使TFT 103导通，同时TFT 102和106的节点α的电位下降以使TFT 105关闭。结果，输出节点的电位变为低电平。

3. 发明授权

US06813332B2 Pulse output circuit, shift register and electronic equipment 有权
标题翻译：脉冲输出电路，移位寄存器和电子设备
公开(公告)号：US06813332B2
公开(公告)日：2004-11-02
申请号：US10756428
申请日：2004-01-14
申请人： Shou Nagao , Yoshifumi Tanada , Yutaka Shionoiri , Hiroyuki Miyake
发明人： Shou Nagao , Yoshifumi Tanada , Yutaka Shionoiri , Hiroyuki Miyake
IPC分类号： G11C1900
CPC分类号： G11C19/28 , G09G3/3688 , G09G2310/0275 , G11C19/00
摘要： A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs 101 and 104 to turn ON the TFTs and a potential of a node &agr; is raised. When the potential of the node &agr; reaches (VDD−VthN), the node &agr; becomes in a floating state. Accordingly, a TFT 105 is turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential of a gate electrode of the TFT 105 is further raised due to an operation of a capacitance means 107 as the potential of the output node is raised, so that the potential of the gate electrode of the TFT 105 becomes higher than (VDD+VthN). Thus, the potential of the output node is raised to VDD without causing a voltage drop due to a threshold voltage of the TFT 105. An output at the subsequent stage is then inputted to a TFT 103 to turn the TFT 103 On, while the potential of the node &agr; of TFTs 102 and 106 is dropped to turn the TFT 105 OFF. As a result, the potential of the output node becomes Low level.
摘要翻译：一种显示装置的驱动电路，其包括单导电类型的TFT并输出具有正常振幅的输出信号。一个脉冲被输入到TFT101和104，使TFT导通，并且提高节点α的电位。当节点α的电位达到（VDD-VthN）时，节点α变为浮动状态。因此，随着时钟信号变为高电平，TFT 105导通，输出节点的电位升高。另一方面，随着输出节点的电位升高，由于电容装置107的操作，TFT 105的栅电极的电位进一步上升，使得TFT 105的栅电极的电位变为高于（VDD + VthN）。因此，输出节点的电位升高到VDD，而不会由于TFT105的阈值电压引起电压降。然后，后级的输出被输入到TFT 103，使TFT 103导通，而电位的TFT102和106的节点α的下降以使TFT 105关闭。结果，输出节点的电位变为低电平。

4. 发明授权

US07116748B2 Pulse output circuit, shift register and electronic equipment 有权
标题翻译：脉冲输出电路，移位寄存器和电子设备
公开(公告)号：US07116748B2
公开(公告)日：2006-10-03
申请号：US10958568
申请日：2004-10-06
申请人： Shou Nagao , Yoshifumi Tanada , Yutaka Shionoiri , Hiroyuki Miyake
发明人： Shou Nagao , Yoshifumi Tanada , Yutaka Shionoiri , Hiroyuki Miyake
IPC分类号： G11C19/00
CPC分类号： G11C19/28 , G09G3/3688 , G09G2310/0275 , G11C19/00
摘要： A driver circuit of a display device, which includes TFTs of a single conductivity type and outputs an output signal with normal amplitude. A pulse is inputted to TFTs 101 and 104 to turn ON the TFTs and a potential of a node α is raised. When the potential of the node α reaches (VDD−VthN), the node α becomes in a floating state. Accordingly, a TFT 105 is turned ON and a potential of an output node is raised as a clock signal becomes High level. On the other hand, a potential of a gate electrode of the TFT 105 is further raised due to an operation of a capacitance means 107 as the potential of the output node is raised, so that the potential of the gate electrode of the TFT 105 becomes higher than (VDD+VthN). Thus, the potential of the output node is raised to VDD without causing a voltage drop due to a threshold voltage of the TFT 105. An output at the subsequent stage is then inputted to a TFT 103 to turn the TFT 103 ON, while the potential of the node α of TFTs 102 and 106 is dropped to turn the TFT 105 OFF. As a result, the potential of the output node becomes Low level.
摘要翻译：一种显示装置的驱动电路，其包括单导电类型的TFT并输出具有正常振幅的输出信号。一个脉冲被输入到TFT101和104，使TFT导通，并且提高节点α的电位。当节点α的电位达到（VDD-VthN）时，节点α变为浮动状态。因此，随着时钟信号变为高电平，TFT 105导通，输出节点的电位升高。另一方面，随着输出节点的电位升高，由于电容装置107的操作，TFT 105的栅电极的电位进一步上升，使得TFT 105的栅电极的电位变为高于（VDD + VthN）。因此，输出节点的电位升高到VDD，而不会由于TFT 105的阈值电压引起电压降。然后，后级的输出被输入到TFT103，使TFT103导通，同时电位的TFT102和106的节点α的下降以使TFT 105关闭。结果，输出节点的电位变为低电平。

5. 发明申请

US20060192699A1 Serial-to-parallel conversion circuit, and semiconductor display device employing the same 有权
公开(公告)号：US20060192699A1
公开(公告)日：2006-08-31
申请号：US11368640
申请日：2006-05-12
申请人： Munehiro Azami , Mitsuaki Osame , Yutaka Shionoiri , Shou Nagao
发明人： Munehiro Azami , Mitsuaki Osame , Yutaka Shionoiri , Shou Nagao
IPC分类号： H03M9/00
CPC分类号： G09G3/3688 , G09G2310/027 , G09G2310/0286 , G09G2310/0289 , H03M9/00
摘要： In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the highest, ½ of the frequency of the input digital data are employed for operating the SPC circuit, whereby the SPC circuit is improved in power dissipation, stability and reliability.

6. 发明授权

US06606045B2 Digital analog converter and electronic device using the same 有权
公开(公告)号：US06606045B2
公开(公告)日：2003-08-12
申请号：US10043306
申请日：2002-01-14
申请人： Munehiro Azami , Mitsuaki Osame , Yutaka Shionoiri , Shou Nagao
发明人： Munehiro Azami , Mitsuaki Osame , Yutaka Shionoiri , Shou Nagao
IPC分类号： H03M166
CPC分类号： G09G3/3275 , G09G3/3233 , G09G3/3648 , G09G3/3688 , G09G2300/0417 , G09G2300/0426 , G09G2300/0842 , G09G2310/027 , G09G2310/0297 , G09G2330/02 , H03M1/0607 , H03M1/68 , H03M1/804
摘要： The present invention relates to a D/A converter circuit which is capable of independently controlling the output voltage amplitude VOUT and the reference voltage. The D/A converter circuit converts “n” bit digital data (“n”: natural number) to analog signals, wherein the respective bits of said “n” bit digital data control a switch, control charge and discharge of electric charges in the capacitance connected to said switch, and output analog signals with the offset potential used as a reference potential.

7. 发明授权

US06420988B1 Digital analog converter and electronic device using the same 有权
公开(公告)号：US06420988B1
公开(公告)日：2002-07-16
申请号：US09449535
申请日：1999-11-29
申请人： Munehiro Azami , Mitsuaki Osame , Yutaka Shionoiri , Shou Nagao
发明人： Munehiro Azami , Mitsuaki Osame , Yutaka Shionoiri , Shou Nagao
IPC分类号： H03M166
CPC分类号： G09G3/3275 , G09G3/3233 , G09G3/3648 , G09G3/3688 , G09G2300/0417 , G09G2300/0426 , G09G2300/0842 , G09G2310/027 , G09G2310/0297 , G09G2330/02 , H03M1/0607 , H03M1/68 , H03M1/804
摘要： The present invention relates to a D/A converter circuit which is capable of independently controlling the output voltage amplitude VOUT and the reference voltage. The D/A converter circuit converts “n” bit digital data (“n”: natural number) to analog signals, wherein the respective bits of said “n” bit digital data control a switch, control charge and discharge of electric charges in the capacitance connected to said switch, and output analog signals with the offset potential used as a reference potential.

8. 发明授权

US07355534B2 Serial-to-parallel conversion circuit, and semiconductor display device employing the same 有权
标题翻译：串行到并行转换电路，以及采用该电路的半导体显示装置
公开(公告)号：US07355534B2
公开(公告)日：2008-04-08
申请号：US11368640
申请日：2006-05-12
申请人： Munehiro Azami , Mitsuaki Osame , Yutaka Shionoiri , Shou Nagao
发明人： Munehiro Azami , Mitsuaki Osame , Yutaka Shionoiri , Shou Nagao
IPC分类号： H03M9/00
CPC分类号： G09G3/3688 , G09G2310/027 , G09G2310/0286 , G09G2310/0289 , H03M9/00
摘要： In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the highest, ½ of the frequency of the input digital data are employed for operating the SPC circuit, whereby the SPC circuit is improved in power dissipation, stability and reliability.
摘要翻译：在将串行输入的数字数据转换为并行数字数据并输出并行数字数据的数字数据的串行 - 并行转换（SPC）电路中，采用输入数字数据的最高频率1/2的频率的时钟信号用于操作SPC电路，由此SPC电路的功率消耗，稳定性和可靠性得到改善。

9. 发明申请

US20050206598A1 Display device and method for operating the same 审中-公开
公开(公告)号：US20050206598A1
公开(公告)日：2005-09-22
申请号：US11115263
申请日：2005-04-27
申请人： Shunpei Yamazaki , Jun Koyama , Masaaki Hiroki , Munehiro Azami , Mitsuaki Osame , Yutaka Shionoiri , Shou Nagao
发明人： Shunpei Yamazaki , Jun Koyama , Masaaki Hiroki , Munehiro Azami , Mitsuaki Osame , Yutaka Shionoiri , Shou Nagao
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G09G3/3651 , G09G3/3688 , G09G2310/027 , G09G2320/0271 , G09G2320/0276 , G09G2320/0285
摘要： To provide a display device capable of displaying a good quality image. According to the present invention, there is provided a display device comprising: a display panel composed of a pixel portion in which a plurality of TFTs are arranged in matrix, a source driver, and a gate driver; an image signal processing circuit for processing an image signal input from an external; and a control circuit for controlling the display panel and the image signal processing circuit, characterized in that the image signal processing circuit corrects the image signal on the basis of a correction table and feeds the display panel with the corrected image signal.

10. 发明授权

US06777273B1 Semiconductor display device 失效
标题翻译：半导体显示装置
公开(公告)号：US06777273B1
公开(公告)日：2004-08-17
申请号：US09309891
申请日：1999-05-11
申请人： Jun Koyama , Hideto Ohnuma , Yutaka Shionoiri , Shou Nagao
发明人： Jun Koyama , Hideto Ohnuma , Yutaka Shionoiri , Shou Nagao
IPC分类号： H01L2100
CPC分类号： H01L27/12 , G02F1/13454 , H01L27/1277
摘要： A small semiconductor display device of low power consumption and with high definition/high resolution/high image quality is provided. The semiconductor display device according to the present invention comprises a pixel matrix circuit, a data line driver circuit and scanning line driver circuits, and these components are formed on the same substrate using a polycrystalline TFT. The fabricating method of the device which includes a process for promoting crystallization by a catalytic element and a process for gettering the catalytic element provides the semiconductor display device with high definition/high resolution/high image quality while it is small in size.
摘要翻译：提供低功耗，高分辨率/高图像质量的小型半导体显示装置。根据本发明的半导体显示装置包括像素矩阵电路，数据线驱动电路和扫描线驱动电路，并且这些部件使用多晶TFT形成在同一基板上。包括催化元件促进结晶的方法的装置的制造方法以及用于吸收催化元件的方法提供了半导体显示装置，其尺寸较小，具有高清晰度/高分辨率/高图像质量。

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