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1. 发明授权

US08059831B2 Noise processing device and method thereof 有权
标题翻译：噪声处理装置及其方法
公开(公告)号：US08059831B2
公开(公告)日：2011-11-15
申请号：US11436574
申请日：2006-05-19
申请人： Shiu-Rong Tong , Tsung-Li Yeh , Yu-Pin Chou , Tzuo-Bo Lin
发明人： Shiu-Rong Tong , Tsung-Li Yeh , Yu-Pin Chou , Tzuo-Bo Lin
IPC分类号： H04B15/00
CPC分类号： H04N5/775 , G11B20/10527 , G11B20/24 , H04N5/4401 , H04N5/602 , H04N5/781 , H04N5/85 , H04N9/7908 , H04N9/8063 , H04N21/4325 , H04N21/439
摘要： A noise processing device and its method are provided for a video/audio system having a high definition multimedia interface (HDMI). The noise processing device includes a detecting unit, a signal generating unit, and a decision unit. The noise processing method includes using the detecting unit to monitor a variation related to an audio signal and generate a detecting signal accordingly; using the signal generating unit to produce an adjustment signal according to the detecting signal; and using the decision unit to produce an output audio signal according to the audio signal and the adjustment signal. Another embodiment of the noise processing device includes a compensation tracking unit having a control unit. The compensation tracking unit produces an output audio signal according to a difference between the output audio signal itself and the audio signal and a gain of the control unit.
摘要翻译：为具有高分辨率多媒体接口（HDMI）的视频/音频系统提供噪声处理装置及其方法。噪声处理装置包括检测单元，信号生成单元和判定单元。噪声处理方法包括使用检测单元来监视与音频信号相关的变化并相应地生成检测信号; 使用所述信号产生单元根据所述检测信号产生调整信号; 以及使用所述判定单元根据所述音频信号和所述调整信号产生输出音频信号。噪声处理装置的另一实施例包括具有控制单元的补偿跟踪单元。补偿跟踪单元根据输出音频信号本身和音频信号之间的差异以及控制单元的增益产生输出音频信号。

2. 发明申请

US20060263064A1 Noise processing device and method thereof 有权
标题翻译：噪声处理装置及其方法
公开(公告)号：US20060263064A1
公开(公告)日：2006-11-23
申请号：US11436574
申请日：2006-05-19
申请人： Shiu-Rong Tong , Tsung-Li Yeh , Yu-Pin Chou , Tzuo-Bo Lin
发明人： Shiu-Rong Tong , Tsung-Li Yeh , Yu-Pin Chou , Tzuo-Bo Lin
IPC分类号： H04N7/00
CPC分类号： H04N5/775 , G11B20/10527 , G11B20/24 , H04N5/4401 , H04N5/602 , H04N5/781 , H04N5/85 , H04N9/7908 , H04N9/8063 , H04N21/4325 , H04N21/439
摘要： A noise processing device and its method are provided for a video/audio system having a high definition multimedia interface (HDMI). The noise processing device includes a detecting unit, a signal generating unit, and a decision unit. The noise processing method includes using the detecting unit to monitor a variation related to an audio signal and generate a detecting signal accordingly; using the signal generating unit to produce an adjustment signal according to the detecting signal; and using the decision unit to produce an output audio signal according to the audio signal and the adjustment signal. Another embodiment of the noise processing device includes a compensation tracking unit having a control unit. The compensation tracking unit produces an output audio signal according to a difference between the output audio signal itself and the audio signal and a gain of the control unit.
摘要翻译：为具有高分辨率多媒体接口（HDMI）的视频/音频系统提供噪声处理装置及其方法。噪声处理装置包括检测单元，信号生成单元和判定单元。噪声处理方法包括使用检测单元来监视与音频信号相关的变化并相应地生成检测信号; 使用所述信号产生单元根据所述检测信号产生调整信号; 以及使用所述判定单元根据所述音频信号和所述调整信号产生输出音频信号。噪声处理装置的另一实施例包括具有控制单元的补偿跟踪单元。补偿跟踪单元根据输出音频信号本身和音频信号之间的差异以及控制单元的增益产生输出音频信号。

3. 发明授权

US08514206B2 Display processing device and timing controller thereof 有权
公开(公告)号：US08514206B2
公开(公告)日：2013-08-20
申请号：US12314601
申请日：2008-12-12
申请人： Yu-Pin Chou , Tzuo-Bo Lin , Ming-Syun Wu
发明人： Yu-Pin Chou , Tzuo-Bo Lin , Ming-Syun Wu
IPC分类号： G09G5/00
CPC分类号： G09G5/006 , G09G5/005 , G09G2370/12
摘要： A timing controller for a display processing device includes: a plurality of predetermined pins for receiving an image signal by a pin-share method, wherein the image signal is a first format image signal or a second format image signal; a detector coupled to the predetermined pins and for detecting at least one of the predetermined pins to determine whether the image signal is the first format image signal or the second format image signal and outputting a detection result; and a processor coupled to the detector and for processing the image signal according to the detection result to generate and output a timing control signal.

4. 发明申请

US20100014621A1 Synchronization Determining Circuit, Receiver Including the Synchronization Determining Circuit, and Method of the Receiver 有权
标题翻译：同步确定电路，包括同步确定电路的接收器和接收器的方法
公开(公告)号：US20100014621A1
公开(公告)日：2010-01-21
申请号：US12501959
申请日：2009-07-13
申请人： Tzuo-Bo Lin , Bing-Juo Chuang , Yu-Pin Chou
发明人： Tzuo-Bo Lin , Bing-Juo Chuang , Yu-Pin Chou
IPC分类号： H04L7/00
CPC分类号： H04L7/10 , G09G5/006 , G09G5/008 , G09G2370/12 , H04L7/046 , H04L25/4908
摘要： A receiver includes; a recovery circuit for receiving an input signal, and generating a data signal and a recovery clock; a processing circuit for processing the data signal to generate a processed signal; and a synchronization determining circuit for determining a synchronization state of the recovery clock according to the processed signal and a first reference value. The data signal includes a synchronous pattern, and the first reference value corresponds to at least a portion of a value in the synchronous pattern processed by the processing circuit. A method of the receiver is also disclosed.
摘要翻译：接收机包括恢复电路，用于接收输入信号，并产生数据信号和恢复时钟; 处理电路，用于处理数据信号以产生处理的信号; 以及同步确定电路，用于根据处理的信号和第一参考值确定恢复时钟的同步状态。数据信号包括同步模式，第一参考值对应于由处理电路处理的同步模式中的值的至少一部分。还公开了接收机的方法。

5. 发明申请

US20090015722A1 SIGNAL RECEIVING CIRCUIT ADAPTED FOR MULTIPLE DIGITAL VIDEO/AUDIO TRANSMISSION INTERFACE STANDARDS 有权
标题翻译：适用于多个数字视频/音频传输接口标准的信号接收电路
公开(公告)号：US20090015722A1
公开(公告)日：2009-01-15
申请号：US12128634
申请日：2008-05-29
申请人： An-Ming Lee , Tzu-Chien Tzeng , Yu-Pin Chou , Tzuo-Bo Lin
发明人： An-Ming Lee , Tzu-Chien Tzeng , Yu-Pin Chou , Tzuo-Bo Lin
IPC分类号： H04N5/44
CPC分类号： H04N5/4401 , H04N5/46 , H04N5/765 , H04N21/42615 , H04N21/4305 , H04N21/436 , H04N21/4363
摘要： The invention provides a signal receiving circuit applied to multiple digital video/audio transmission interface standards. The signal receiving circuit includes at least an input interface for receiving an input signal, and at least an interface circuit. The input interface includes a set of shared input terminals, a set of first separate input terminals for receiving an input signal corresponding to a first transmission specification with the set of shared input terminals, and a set of second separate input terminals for receiving an input signal corresponding to a second transmission specification with the set of shared input terminals. The interface circuit includes a control circuit coupled to the input interface for supplying a control signal, and a processing module coupled to the input interface and the control circuit for processing the input signal according to the control signal to generate an output signal.
摘要翻译：本发明提供一种应用于多个数字视频/音频传输接口标准的信号接收电路。信号接收电路至少包括用于接收输入信号的输入接口和至少一个接口电路。输入接口包括一组共享输入端子，一组第一分离输入端子，用于接收与该组共享输入端子对应的第一传输规格的输入信号，以及一组用于接收输入信号的第二单独输入端子对应于具有该组共享输入端的第二传输规范。接口电路包括耦合到用于提供控制信号的输入接口的控制电路，以及耦合到输入接口和控制电路的处理模块，用于根据控制信号处理输入信号以产生输出信号。

6. 发明授权

US07945706B2 Signal receiving circuit adapted for multiple digital video/audio transmission interface standards 有权
标题翻译：信号接收电路适用于多个数字视频/音频传输接口标准
公开(公告)号：US07945706B2
公开(公告)日：2011-05-17
申请号：US12128634
申请日：2008-05-29
申请人： An-Ming Lee , Tzu-Chien Tzeng , Yu-Pin Chou , Tzuo-Bo Lin
发明人： An-Ming Lee , Tzu-Chien Tzeng , Yu-Pin Chou , Tzuo-Bo Lin
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： H04N5/4401 , H04N5/46 , H04N5/765 , H04N21/42615 , H04N21/4305 , H04N21/436 , H04N21/4363
摘要： The invention provides a signal receiving circuit applied to multiple digital video/audio transmission interface standards. The signal receiving circuit includes at least an input interface for receiving an input signal, and at least an interface circuit. The input interface includes a set of shared input terminals, a set of first separate input terminals for receiving an input signal corresponding to a first transmission specification with the set of shared input terminals, and a set of second separate input terminals for receiving an input signal corresponding to a second transmission specification with the set of shared input terminals. The interface circuit includes a control circuit coupled to the input interface for supplying a control signal, and a processing module coupled to the input interface and the control circuit for processing the input signal according to the control signal to generate an output signal.
摘要翻译：本发明提供一种应用于多个数字视频/音频传输接口标准的信号接收电路。信号接收电路至少包括用于接收输入信号的输入接口和至少一个接口电路。输入接口包括一组共享输入端子，一组第一分离输入端子，用于接收与该组共享输入端子对应的第一传输规格的输入信号，以及一组用于接收输入信号的第二单独输入端子对应于具有该组共享输入端的第二传输规范。接口电路包括耦合到用于提供控制信号的输入接口的控制电路，以及耦合到输入接口和控制电路的处理模块，用于根据控制信号处理输入信号以产生输出信号。

7. 发明申请

US20100188574A1 DEVICE AND METHOD FOR CONTROLLING FRAME INPUT AND OUTPUT 有权
标题翻译：用于控制框架输入和输出的装置和方法
公开(公告)号：US20100188574A1
公开(公告)日：2010-07-29
申请号：US12692389
申请日：2010-01-22
申请人： Chia-Lung HUNG , Tzuo-Bo Lin , Hsien-Chun Chang , Yu-Pin Chou
发明人： Chia-Lung HUNG , Tzuo-Bo Lin , Hsien-Chun Chang , Yu-Pin Chou
IPC分类号： H04N9/64 , H04N5/04
CPC分类号： H04N7/0105 , H04N7/0132
摘要： A device and method for controlling frame input and output are applied to the reception of image data from a source device and output of the image data to a destination device, the device includes a buffer, a buffer control circuit, and a frame write controller. The input pixel clock is not equal to the output pixel clock. The frame write controller generates a write permission signal according to the Input DE and the Output DE. The buffer control circuit generates a write control signal according to the Input DE and the write permission signal, and generates a read control signal according to the Output DE. The buffer receives the image data from the source device according to the write control signal and the input pixel clock, and outputs the image data to the destination device according to the read control signal and the output pixel clock.
摘要翻译：用于控制帧输入和输出的装置和方法被应用于从源设备接收图像数据并将图像数据输出到目的地设备，该设备包括缓冲器，缓冲器控制电路和帧写入控制器。输入像素时钟不等于输出像素时钟。帧写入控制器根据输入DE和输出DE生成写许可信号。缓冲器控制电路根据输入DE和写允许信号产生写控制信号，并根据输出DE生成读控制信号。缓冲器根据写控制信号和输入像素时钟从源装置接收图像数据，并根据读控制信号和输出像素时钟将图像数据输出到目的地装置。

8. 发明授权

US07372298B2 Chip with adjustable pinout function and method thereof 有权
标题翻译：具有可调引脚排列功能的芯片及其方法
公开(公告)号：US07372298B2
公开(公告)日：2008-05-13
申请号：US11277361
申请日：2006-03-24
申请人： Hung-Jen Chu , Chao-Hsin Lu , Shiu-Rong Tong , Yu-Pin Chou
发明人： Hung-Jen Chu , Chao-Hsin Lu , Shiu-Rong Tong , Yu-Pin Chou
IPC分类号： H03K19/173 , H03K19/00
CPC分类号： G06F1/22 , H03K19/1732
摘要： A chip with an adjustable pinout function is disclosed. The chip includes a first pinout, a second pinout, a logic circuit, and a selecting circuit. The logic circuit includes a first port and a second port. The selecting circuit, which is coupled to the logic circuit, the first pinout, and the second pinout, controls the first pinout to be coupled to the first port or the second port, and controls the second pinout to be coupled to the first port or the second port.
摘要翻译：公开了一种具有可调节引脚排列功能的芯片。芯片包括第一引脚，第二引脚，逻辑电路和选择电路。逻辑电路包括第一端口和第二端口。耦合到逻辑电路，第一引脚排列和第二引脚分布的选择电路控制第一引脚被耦合到第一端口或第二端口，并且控制第二引脚分布以耦合到第一端口或第二个港口。

9. 发明申请

US20060220687A1 CHIP WITH ADJUSTABLE PINOUT FUNCTION AND METHOD THEREOF 有权
标题翻译：具有可调节引脚功能的芯片及其方法
公开(公告)号：US20060220687A1
公开(公告)日：2006-10-05
申请号：US11277361
申请日：2006-03-24
申请人： Hung-Jen Chu , Chao-Hsin Lu , Shiu-Rong Tong , Yu-Pin Chou
发明人： Hung-Jen Chu , Chao-Hsin Lu , Shiu-Rong Tong , Yu-Pin Chou
IPC分类号： H03K19/00
CPC分类号： G06F1/22 , H03K19/1732
摘要： A chip with an adjustable pinout function is disclosed. The chip includes a first pinout, a second pinout, a logic circuit, and a selecting circuit. The logic circuit includes a first port and a second port. The selecting circuit, which is coupled to the logic circuit, the first pinout, and the second pinout, controls the first pinout to be coupled to the first port or the second port, and controls the second pinout to be coupled to the first port or the second port.
摘要翻译：公开了一种具有可调节引脚排列功能的芯片。芯片包括第一引脚，第二引脚，逻辑电路和选择电路。逻辑电路包括第一端口和第二端口。耦合到逻辑电路，第一引脚排列和第二引脚分布的选择电路控制第一引脚被耦合到第一端口或第二端口，并且控制第二引脚分布以耦合到第一端口或第二个港口。

10. 发明申请

US20050275612A1 Liquid Crystal Display Capable of Reducing Flicker and Method Thereof 审中-公开
标题翻译：能够减少闪烁的液晶显示器及其方法
公开(公告)号：US20050275612A1
公开(公告)日：2005-12-15
申请号：US11160229
申请日：2005-06-14
申请人： Yu-Pin Chou , Shiu-Rong Tong , Wen- Hsia Kung
发明人： Yu-Pin Chou , Shiu-Rong Tong , Wen- Hsia Kung
IPC分类号： G09G3/36
CPC分类号： G09G3/3614 , G09G3/3648 , G09G3/3688 , G09G2320/0247
摘要： A method for controlling an LCD to display an image. The method includes receiving a display data flow, generating a polarity signal, generating a gray-scale signal according to the polarity signal and the display data flow, and driving a pixel unit to display image according to the gray-scale signal. The polarity signal is substantially DC-balanced. A display utilizing such method may reduce the influence of flicker phenomenon.
摘要翻译：一种用于控制LCD以显示图像的方法。该方法包括接收显示数据流，产生极性信号，根据极性信号和显示数据流产生灰度信号，并驱动像素单元根据灰度信号显示图像。极性信号基本上是直流平衡的。利用这种方法的显示器可以减少闪烁现象的影响。

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