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1. 发明申请

US20090140818A1 PHASE-LOCKED LOOP CIRCUIT AND DATA REPRODUCTION APPARATUS 有权
标题翻译：相位锁定环路和数据传输装置
公开(公告)号：US20090140818A1
公开(公告)日：2009-06-04
申请号：US12363156
申请日：2009-01-30
申请人： Shinichi Yamane , Seiji Watanabe
发明人： Shinichi Yamane , Seiji Watanabe
IPC分类号： H03L7/08
CPC分类号： H03L7/085 , H03L7/0807 , H03L7/087 , H03L7/0898 , H04L7/0087
摘要： This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functions, i.e., phase and duty adjustments for binarized data, the phase comparison with one edge is performed only at the phase adjustment by means of a phase-locked loop circuit 33 having an edge switching means 4 which controls the phase comparator 1. The phase comparator 1 inputs the binarized and a bit synchronous clock, and switches the output between a comparison result with one edge, i.e., a rising edge or a falling edge of binarized data, and a comparison result with both edges.
摘要翻译：本发明涉及一种可以减少在数据再现装置中进行初始调整所需的处理时间的锁相环电路和数据再现装置。在具有两个控制功能（即二进制数据的相位和占空比调整）的数字数据再现装置中，仅通过具有边沿切换装置4的锁相环电路33在相位调整时执行与一个边沿的相位比较其控制相位比较器1.相位比较器1输入二进制和位同步时钟，并且在一个比较结果与一个边沿之间切换输出，即二值化数据的上升沿或下降沿，以及与两边。

2. 发明授权

US07362186B2 Phase-locked loop circuit and data reproduction apparatus 有权
标题翻译：锁相环电路和数据再现装置
公开(公告)号：US07362186B2
公开(公告)日：2008-04-22
申请号：US11375814
申请日：2006-03-15
申请人： Shinichi Yamane , Seiji Watanabe
发明人： Shinichi Yamane , Seiji Watanabe
IPC分类号： H03L7/00
CPC分类号： H03L7/085 , H03L7/0807 , H03L7/087 , H03L7/0898 , H04L7/0087
摘要： This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functions, i.e., phase and duty adjustments for binarized data, the phase comparison with one edge is performed only at the phase adjustment by means of a phase-locked loop circuit 33 having an edge switching means 4 which controls the phase comparator 1. The phase comparator 1 inputs the binarized and a bit synchronous clock, and switches the output between a comparison result with one edge, i.e., a rising edge or a falling edge of binarized data, and a comparison result with both edges.
摘要翻译：本发明涉及一种可以减少在数据再现装置中进行初始调整所需的处理时间的锁相环电路和数据再现装置。在具有两个控制功能（即二进制数据的相位和占空比调整）的数字数据再现装置中，仅通过具有边沿切换装置4的锁相环电路33在相位调整时执行与一个边沿的相位比较其控制相位比较器1。相位比较器1输入二进制和位同步时钟，并且在一个比较结果与一个边缘之间切换输出，即二值化数据的上升沿或下降沿，以及两个边沿的比较结果。

3. 发明申请

US20070279134A1 Phase-locked loop circuit and data reproduction apparatus 有权
标题翻译：锁相环电路和数据再现装置
公开(公告)号：US20070279134A1
公开(公告)日：2007-12-06
申请号：US11805556
申请日：2007-05-23
申请人： Shinichi Yamane , Seiji Watanabe
发明人： Shinichi Yamane , Seiji Watanabe
IPC分类号： H03L7/08
CPC分类号： H03L7/085 , H03L7/0807 , H03L7/087 , H03L7/0898 , H04L7/0087
摘要： This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functions, i.e., phase and duty adjustments for binarized data, the phase comparison with one edge is performed only at the phase adjustment by means of a phase-locked loop circuit 33 having an edge switching means 4 which controls the phase comparator 1. The phase comparator 1 inputs the binarized and a bit synchronous clock, and switches the output between a comparison result with one edge, i.e., a rising edge or a falling edge of binarized data, and a comparison result with both edges.
摘要翻译：本发明涉及一种可以减少在数据再现装置中进行初始调整所需的处理时间的锁相环电路和数据再现装置。在具有两个控制功能的数字数据再现装置中，即用于二值化数据的相位和占空比调整，仅通过具有边沿切换装置4的锁相环电路33在相位调整时执行与一个边沿的相位比较其控制相位比较器1.相位比较器1输入二进制和位同步时钟，并且在一个比较结果与一个边沿之间切换输出，即二值化数据的上升沿或下降沿，以及与两边。

4. 发明授权

US07034622B2 Phase-locked loop circuit and data reproduction apparatus 有权
标题翻译：锁相环电路和数据再现装置
公开(公告)号：US07034622B2
公开(公告)日：2006-04-25
申请号：US10881883
申请日：2004-06-30
申请人： Shinichi Yamane , Seiji Watanabe
发明人： Shinichi Yamane , Seiji Watanabe
IPC分类号： H03L7/00
CPC分类号： H03L7/085 , H03L7/0807 , H03L7/087 , H03L7/0898 , H04L7/0087
摘要： This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functions, i.e., phase and duty adjustments for binarized data, the phase comparison with one edge is performed only at the phase adjustment by means of a phase-locked loop circuit 33 having an edge switching means 4 which controls the phase comparator 1. The phase comparator 1 inputs the binarized and a bit synchronous clock, and switches the output between a comparison result with one edge, i.e., a rising edge or a falling edge of binarized data, and a comparison result with both edges.
摘要翻译：本发明涉及一种可以减少在数据再现装置中进行初始调整所需的处理时间的锁相环电路和数据再现装置。在具有两个控制功能（即二进制数据的相位和占空比调整）的数字数据再现装置中，仅通过具有边沿切换装置4的锁相环电路33在相位调整时执行与一个边沿的相位比较其控制相位比较器1。相位比较器1输入二进制和位同步时钟，并且在一个比较结果与一个边缘之间切换输出，即二值化数据的上升沿或下降沿，以及两个边沿的比较结果。

5. 发明申请

US20060176089A1 Phase-locked loop circuit and data reproduction apparatus 有权
公开(公告)号：US20060176089A1
公开(公告)日：2006-08-10
申请号：US11375814
申请日：2006-03-15
申请人： Shinichi Yamane , Seiji Watanabe
发明人： Shinichi Yamane , Seiji Watanabe
IPC分类号： H03L7/06
CPC分类号： H03L7/085 , H03L7/0807 , H03L7/087 , H03L7/0898 , H04L7/0087
摘要： This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functions, i.e., phase and duty adjustments for binarized data, the phase comparison with one edge is performed only at the phase adjustment by means of a phase-locked loop circuit 33 having an edge switching means 4 which controls the phase comparator 1. The phase comparator 1 inputs the binarized and a bit synchronous clock, and switches the output between a comparison result with one edge, i.e., a rising edge or a falling edge of binarized data, and a comparison result with both edges.

6. 发明授权

US07501902B2 Phase-locked loop circuit and data reproduction apparatus 有权
标题翻译：锁相环电路和数据再现装置
公开(公告)号：US07501902B2
公开(公告)日：2009-03-10
申请号：US11805556
申请日：2007-05-23
申请人： Shinichi Yamane , Seiji Watanabe
发明人： Shinichi Yamane , Seiji Watanabe
IPC分类号： H03L7/00
CPC分类号： H03L7/085 , H03L7/0807 , H03L7/087 , H03L7/0898 , H04L7/0087
摘要： This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functions, i.e., phase and duty adjustments for binarized data, the phase comparison with one edge is performed only at the phase adjustment by means of a phase-locked loop circuit 33 having an edge switching means 4 which controls the phase comparator 1. The phase comparator 1 inputs the binarized and a bit synchronous clock, and switches the output between a comparison result with one edge, i.e., a rising edge or a falling edge of binarized data, and a comparison result with both edges.
摘要翻译：本发明涉及一种可以减少在数据再现装置中进行初始调整所需的处理时间的锁相环电路和数据再现装置。在具有两个控制功能的数字数据再现装置中，即用于二值化数据的相位和占空比调整，仅通过具有边沿切换装置4的锁相环电路33在相位调整时执行与一个边沿的相位比较其控制相位比较器1.相位比较器1输入二进制和位同步时钟，并且在一个比较结果与一个边沿之间切换输出，即二值化数据的上升沿或下降沿，以及与两边。

7. 发明授权

US06828865B2 Phase-locked loop circuit and data reproduction apparatus 有权
公开(公告)号：US06828865B2
公开(公告)日：2004-12-07
申请号：US10197021
申请日：2002-07-17
申请人： Shinichi Yamane , Seiji Watanabe
发明人： Shinichi Yamane , Seiji Watanabe
IPC分类号： H03L700
CPC分类号： H03L7/085 , H03L7/0807 , H03L7/087 , H03L7/0898 , H04L7/0087
摘要： This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functions, i.e., phase and duty adjustments for binarized data, the phase comparison with one edge is performed only at the phase adjustment by means of a phase-locked loop circuit 33 having an edge switching means 4 which controls the phase comparator 1. The phase comparator 1 inputs the binarized and a bit synchronous clock, and switches the output between a comparison result with one edge, i.e., a rising edge or a falling edge of binarized data, and a comparison result with both edges.

8. 发明申请

US20080019918A1 Medicinal Preparation 审中-公开
标题翻译：药用制剂
公开(公告)号：US20080019918A1
公开(公告)日：2008-01-24
申请号：US11662208
申请日：2005-09-07
申请人： Takao Aoki , Shinichi Yamane , Shinichi Kawanami , Yuichi Koyamatsu , Yoshifumi Watanabe , Itaru Hamachi , Ryo Suzuki , Masakazu Koiwa , Nobuo Ida
发明人： Takao Aoki , Shinichi Yamane , Shinichi Kawanami , Yuichi Koyamatsu , Yoshifumi Watanabe , Itaru Hamachi , Ryo Suzuki , Masakazu Koiwa , Nobuo Ida
IPC分类号： A61K49/06 , A61K31/70 , A61K31/7016 , A61K9/14 , A61K9/00 , A61K38/02
CPC分类号： A61K49/1839 , A61K47/549 , A61K47/6937 , A61K49/0043 , A61K49/0093 , A61K49/1887
摘要： A pharmaceutical preparation has a ligand structure specifically recognizing a target site and an amphiphilic compound having a hydrophobic or amphiphilic group. The pharmaceutical preparation employs an amphiphilic compound of specific structure obtained by introducing a chained hydrophilic group with an appropriate flexibility, and thus becomes a fine particle suited for drug targeting. The pharmaceutical preparation is expected to give a prolonged pharmacological effect. A particulate preparation exhibiting a remarkable site targeting property can be formed. Further, according to the selection of matrix forming material, the drug releasing property can be controlled.
摘要翻译：药物制剂具有特异性识别靶位点的配体结构和具有疏水或两亲基团的两亲化合物。药物制剂使用通过引入具有适当柔性的链状亲水基团而获得的具有特定结构的两亲化合物，从而成为适合于药物靶向的细小颗粒。药物制剂预期会延长药理作用。可以形成表现出显着的位置靶向性的微粒制剂。此外，根据基质形成材料的选择，可以控制药物释放性。

9. 发明申请

US20120253082A1 METHOD OF PRODUCING DIOL OR TRIOL 有权
标题翻译：生产二醇或三氟乙酸的方法
公开(公告)号：US20120253082A1
公开(公告)日：2012-10-04
申请号：US13076053
申请日：2011-03-30
申请人： Izumi MORITA , Masateru Ito , Hideki Sawai , Shinichi Minegishi , Katsushige Yamada , Kenji Kawamura , Shinichi Yamane
发明人： Izumi MORITA , Masateru Ito , Hideki Sawai , Shinichi Minegishi , Katsushige Yamada , Kenji Kawamura , Shinichi Yamane
IPC分类号： C07C29/76
CPC分类号： C07C29/76 , C07C31/202 , C07C31/205 , C07C31/207 , C07C31/225
摘要： A method for producing a diol or triol, which has a step of removing impurities contained in a diol- or triol-containing solution, is provided. In the method, a diol- or triol-containing solution is filtered through a nanofiltration membrane having a polyamide-containing functional layer. The diol- or triol-containing solution is then collected from the permeate flow of the nanofiltration membrane.
摘要翻译：提供了一种制备二醇或三醇的方法，其具有除去二醇或三醇溶液中所含杂质的步骤。在该方法中，通过具有含聚酰胺功能层的纳滤膜过滤二醇或三醇溶液。然后从纳滤膜的渗透流中收集含二醇或三醇的溶液。

10. 发明授权

US07777767B2 Image forming apparatus and method of adjusting color shift 有权
标题翻译：图像形成装置及调色方法
公开(公告)号：US07777767B2
公开(公告)日：2010-08-17
申请号：US11592051
申请日：2006-11-01
申请人： Norio Tomita , Yoshikazu Harada , Kengo Matsuyama , Shinichi Yamane
发明人： Norio Tomita , Yoshikazu Harada , Kengo Matsuyama , Shinichi Yamane
IPC分类号： B41J2/385 , B41J2/47 , B41J2/435 , G01D15/14
CPC分类号： G03G15/5033 , G03G15/011 , G03G15/0194 , G03G2215/0119 , G03G2215/0161
摘要： An image forming apparatus includes an image forming unit that forms a color image in which a plurality of color component images are superimposed; and a formation controlling unit that allows the image forming unit to form images for adjustment of formation positions of the respective color component images. The formation controlling unit allows the image forming unit to form, for each color, a plurality of adjustment images having different tilts with respect to a main scanning direction. A shift of a detected position of each adjustment image from a reference position in which each adjustment image should be formed is calculated, a tilt and an intercept of a regression line that uses the reference positions and the calculated shifts as variables are calculated, and a shift in the main scanning direction and a shift in a sub-scanning direction are determined based on the calculated tilt and intercept.
摘要翻译：图像形成装置包括：图像形成单元，其形成多个彩色分量图像重叠的彩色图像; 以及形成控制单元，其允许图像形成单元形成用于调整各个颜色分量图像的形成位置的图像。形成控制单元允许图像形成单元针对每种颜色形成相对于主扫描方向具有不同倾斜的多个调整图像。计算出每个调整图像的检测位置从其中应形成每个调整图像的参考位置的偏移，计算使用参考位置和计算的位移作为变量的回归线的倾斜和截距，并且基于计算出的倾斜和截距来确定主扫描方向上的偏移和副扫描方向的偏移。

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