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1. 发明授权

US5097310A Complementary semiconductor device having improved device isolating region 失效
标题翻译：具有改进的器件隔离区域的补充半导体器件
公开(公告)号：US5097310A
公开(公告)日：1992-03-17
申请号：US409379
申请日：1989-09-19
申请人： Takahisa Eimori , Wataru Wakamiya , Hiroji Ozaki , Yoshinori Tanaka , Shinichi Satoh
发明人： Takahisa Eimori , Wataru Wakamiya , Hiroji Ozaki , Yoshinori Tanaka , Shinichi Satoh
IPC分类号： H01L21/761 , H01L21/76 , H01L27/08 , H01L27/092 , H01L29/78
CPC分类号： H01L27/0928
摘要： A complementary semiconductor device having an improved capability of isolating devices comprises a P well 3 and an N well 2 both formed adjacent to each other on a main surface of a substrate 1, an N type impurity layer formed in the P well 8 on the main surface of the substrate, a P type impurity layer formed in the N well 9 on the main surface of the substrate, an N type region formed at the junction of the N well and the P well 71 on the main surface of the substrate, a first shield electrode 52 formed between the N type impurity layer 8 and the N type region 71 on the main surface of the substrate through an insulating film and a second shield electrode 51 formed between the N type region 71 and the P type impurity layer 9 on the main surface of the substrate through an insulating film. The first shield electrode 52 is connected to a potential V.sub.SS and the second shield electrode 51 and the N type region 71 are connected to a potential V.sub.CC, so that an N channel MOS transistor 101 comprising the first shield electrode 52 does not turn on and a device comprising the second shield electrode does not form a field effect transistor.
摘要翻译：具有改进的隔离装置能力的互补半导体器件包括在衬底1的主表面上彼此相邻形成的P阱3和N阱2，形成在主衬底1上的P阱8中的N型杂质层在基板的主表面上形成在N阱9中的P型杂质层，形成在基板主表面上的N阱和P阱71的接合部的N型区域，第一屏蔽电极52，其通过绝缘膜形成在基板的主表面上的N型杂质层8和N型区域71之间，形成在N型区域71和P型杂质层9之间的第二屏蔽电极51，基板的主表面通过绝缘膜。第一屏蔽电极52连接到电位VSS，第二屏蔽电极51和N型区域71连接到电位VCC，使得包括第一屏蔽电极52的N沟道MOS晶体管101不导通，包括第二屏蔽电极的装置不形成场效应晶体管。

2. 发明授权

US5225704A Field shield isolation structure for semiconductor memory device and method for manufacturing the same 失效
标题翻译：半导体存储器件的场屏蔽隔离结构及其制造方法
公开(公告)号：US5225704A
公开(公告)日：1993-07-06
申请号：US614963
申请日：1990-11-19
申请人： Wataru Wakamiya , Shinichi Satoh , Hiroji Ozaki , Takahisa Eimori , Yoshinori Tanaka
发明人： Wataru Wakamiya , Shinichi Satoh , Hiroji Ozaki , Takahisa Eimori , Yoshinori Tanaka
IPC分类号： H01L27/108
CPC分类号： H01L27/10805
摘要： In a DRAM having stacked capacitor cells, elements are isolated by field shield isolating structure. The field shield isolating structure is formed surrounding both X and Y directions of the memory cell in the DRAM. The field shield isolating structure comprises an isolating electrode layer formed on a semiconductor substrate between adjacent memory cells with an insulating film interposed therebetween. Two impurity regions included in the adjacent memory cells and the isolating electrode layer constitute a MOS transistor. A voltage for maintaining the MOS transistor normally-off is applied to the isolating electrode layer. A portion of the stacked capacitor extends to the isolating electrode layer. One of the source/drain regions of the MOS transistor is formed in self-alignment, using a sidewall spacer formed of an insulating film on a sidewall of the field shield electrode as a mask.
摘要翻译：在具有层叠电容器单元的DRAM中，通过场屏蔽隔离结构来隔离元件。在DRAM中的存储单元的X和Y方向上形成场屏蔽隔离结构。场屏蔽隔离结构包括在相邻的存储单元之间的半导体衬底上形成有绝缘膜的隔离电极层。包括在相邻存储单元和隔离电极层中的两个杂质区构成MOS晶体管。用于保持MOS晶体管常闭的电压被施加到隔离电极层。层叠电容器的一部分延伸到隔离电极层。使用由场屏蔽电极的侧壁上的绝缘膜形成的侧壁间隔作为掩模，自对准地形成MOS晶体管的源/漏区之一。

3. 发明授权

US5181094A Complementary semiconductor device having improved device isolating region 失效
标题翻译：具有改进的器件隔离区域的互补半导体器件
公开(公告)号：US5181094A
公开(公告)日：1993-01-19
申请号：US783029
申请日：1991-10-25
申请人： Takahisa Eimori , Wataru Wakamiya , Hiroji Ozaki , Yoshinori Tanaka , Shinichi Satoh
发明人： Takahisa Eimori , Wataru Wakamiya , Hiroji Ozaki , Yoshinori Tanaka , Shinichi Satoh
IPC分类号： H01L27/092
CPC分类号： H01L27/0928 , H01L2924/0002
摘要： A complementary semiconductor device having an improved capability of isolating devices comprises a P well 3 and an N well 2 both formed adjacent to each other on a main surface of a substrate 1, an N type impurity layer formed in the P well 8 on the main surface of the substrate, a P type impurity layer formed in the N well 9 on the main surface of the substrate, an N type region formed at the junction of the N well and the P well 71 on the main surface of the substrate, a first shield electrode 52 formed between the N type impurity layer 8 and the N type region 71 on the main surface of the substrate through an insulating film and a second shield electrode 51 formed between the N type region 71 and the P type impurity layer 9 on the main surface of the substrate through an insulating film. The first shield electrode 52 is connected to a potential V.sub.SS and the second shield electrode 51 and the N type region 71 are connected to a potential V.sub.CC, so that an N channel MOS transistor 101 comprising the first shield electrode 52 does not turn on and a device comprising the second shield electrode does not form a field effect transistor.
摘要翻译：具有改进的隔离装置能力的互补半导体器件包括在衬底1的主表面上彼此相邻形成的P阱3和N阱2，形成在主衬底1上的P阱8中的N型杂质层在基板的主表面上形成在N阱9中的P型杂质层，形成在基板主表面上的N阱和P阱71的接合部的N型区域，第一屏蔽电极52通过绝缘膜形成在基板的主表面上的N型杂质层8和N型区域71之间，形成在N型区域71和P型杂质层9之间的第二屏蔽电极51 基板的主表面通过绝缘膜。第一屏蔽电极52连接到电位VSS，第二屏蔽电极51和N型区域71连接到电位VCC，使得包括第一屏蔽电极52的N沟道MOS晶体管101不导通，包括第二屏蔽电极的装置不形成场效应晶体管。

4. 发明授权

US5094965A Field effect transistor having substantially coplanar surface structure and a manufacturing method therefor 失效
标题翻译：具有大面积共面表面结构的场效应晶体管及其制造方法
公开(公告)号：US5094965A
公开(公告)日：1992-03-10
申请号：US606276
申请日：1990-10-31
申请人： Hiroji Ozaki , Takahisa Eimori , Yoshinori Tanaka , Wataru Wakamiya , Shinichi Satoh
发明人： Hiroji Ozaki , Takahisa Eimori , Yoshinori Tanaka , Wataru Wakamiya , Shinichi Satoh
IPC分类号： H01L21/3205 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/417
CPC分类号： H01L29/41775 , H01L27/10808
摘要： A semiconductor device has MOS field effect transistors isolated by a field shield. The field shield has a gate of conductor layers formed spaced apart from each other on a silicon substrate through an insulating film and with the surface thereof being covered with an insulating film. In regions isolated by the field shield, MOS field effect transistors are formed. Each of the MOS field effect transistors has a gate electrode of a conductor layer formed on the silicon substrate through an insulating film and with the surface thereof being covered with an insulating film. An impurity diffused region is formed in a region on the silicon substrate between the gate electrode and the field shield. A portion on an exposed surface of the impurity diffused region between the field shield and the gate electrode is selectively filled with a tungsten buried layer. The tungsten buried layer is formed, flattened relative to the gate electrode and the gate constituting the field shield.

5. 发明授权

US5930614A Method for forming MOS device having field shield isolation 失效
标题翻译：用于形成具有场屏蔽隔离的MOS器件的方法
公开(公告)号：US5930614A
公开(公告)日：1999-07-27
申请号：US765771
申请日：1991-09-26
申请人： Takahisa Eimori , Shinichi Satoh , Wataru Wakamiya , Hiroji Ozaki , Yoshinori Tanaka
发明人： Takahisa Eimori , Shinichi Satoh , Wataru Wakamiya , Hiroji Ozaki , Yoshinori Tanaka
IPC分类号： H01L21/76 , H01L21/765 , H01L29/78 , H01L21/8238
CPC分类号： H01L21/765
摘要： A first conductor for a field shield and a first insulating film are sequentially formed in a predetermined shape on a major surface of a P-type semiconductor substrate through an insulating film. A third insulating film is formed over the semiconductor substrate so as to cover the first conductor and a second insulating film thereon. The third insulating film is anisotropically etched, so that a sidewall insulating film is formed on sidewalls of the first conductor. Second and third conductors respectively serving as gate electrodes of field effect transistors are formed through a fourth insulating film. n-type impurities are implanted into the major surface of the semiconductor substrate utilizing as masks the first insulating film, the sidewall oxide film, the second conductor and the third conductor and are diffused, to form impurity regions. Since the sidewall oxide film is thick, the impurity regions are not overlapped even by diffusion with a portion where the first conductor is projected on the semiconductor substrate. Thus, a threshold voltage of a field shield transistor comprising the first conductor and the impurity regions on both sides thereof is raised, so that isolation characteristics of the field shield is improved.
摘要翻译：用于场屏蔽和第一绝缘膜的第一导体通过绝缘膜在P型半导体衬底的主表面上依次形成为预定形状。在半导体衬底上形成第三绝缘膜，以覆盖第一导体和第二绝缘膜。第三绝缘膜被各向异性地蚀刻，从而在第一导体的侧壁上形成侧壁绝缘膜。分别用作场效晶体管的栅极的第二和第三导体通过第四绝缘膜形成。利用第一绝缘膜，侧壁氧化物膜，第二导体和第三导体作为掩模将n型杂质注入到半导体衬底的主表面中，并扩散，形成杂质区。由于侧壁氧化物膜厚，因此即使通过第一导体投射在半导体基板上的部分的扩散也不会使杂质区域重叠。因此，包括第一导体和其两侧的杂质区域的场屏蔽晶体管的阈值电压升高，从而提高了场屏蔽的隔离特性。

6. 发明授权

US5521419A Semiconductor device having field shield element isolating structure and method of manufacturing the same 失效
标题翻译：具有场屏蔽元件隔离结构的半导体器件及其制造方法
公开(公告)号：US5521419A
公开(公告)日：1996-05-28
申请号：US327341
申请日：1994-10-21
申请人： Wataru Wakamiya , Shinichi Satoh , Hiroji Ozaki , Takahisa Eimori , Yoshinori Tanaka
发明人： Wataru Wakamiya , Shinichi Satoh , Hiroji Ozaki , Takahisa Eimori , Yoshinori Tanaka
IPC分类号： H01L21/76 , H01L21/8242 , H01L23/528 , H01L27/10 , H01L27/108 , H01L29/78 , H01L29/76
CPC分类号： H01L27/10852 , H01L23/5283 , H01L27/10808 , H01L2924/0002
摘要： A field shield isolating structure forms a structure for isolating elements of a semiconductor device. The field shield isolating structure includes a field shield gate insulating film and field shield electrode formed on the semiconductor substrate in separate processes to constitute a quasi-MOS transistor using impurity regions of adjacent MOS transistors. The film thickness of the field shield gate insulating film is set arbitrarily, the threshold voltage of the quasi-MOS transistor is set high, and then elements are insulated and isolated, so that the transistor is operated in the off state. The upper surface of the field shield electrode is also covered with the upper insulating film. The thicknesses of the upper insulating film and of the field shield gate insulating film is adjusted to have such values that prevent turning ON of the MOS transistor by the capacitance divided voltage. The voltage may be applied from upper conductive layers such as word lines formed above the upper insulating film.
摘要翻译：场屏蔽隔离结构形成用于隔离半导体器件的元件的结构。场屏蔽隔离结构包括在单独的工艺中形成在半导体衬底上的场屏蔽栅极绝缘膜和场屏蔽电极，以使用相邻MOS晶体管的杂质区构成准MOS晶体管。场屏蔽栅极绝缘膜的膜厚度是任意设定的，准MOS晶体管的阈值电压被设定为高，然后元件被绝缘和隔离，使晶体管工作在关闭状态。场屏蔽电极的上表面也被上绝缘膜覆盖。将上绝缘膜和场屏蔽栅极绝缘膜的厚度调整为具有防止MOS晶体管导通的电容分压的值。可以从形成在上绝缘膜上方的字线等上导电层施加电压。

7. 发明授权

US4994893A Field effect transistor substantially coplanar surface structure 失效
标题翻译：场效应晶体管基本上共面的表面结构
公开(公告)号：US4994893A
公开(公告)日：1991-02-19
申请号：US405284
申请日：1989-09-11
申请人： Hiroji Ozaki , Takahisa Eimori , Yoshinori Tanaka , Wataru Wakamiya , Shinichi Satoh
发明人： Hiroji Ozaki , Takahisa Eimori , Yoshinori Tanaka , Wataru Wakamiya , Shinichi Satoh
IPC分类号： H01L21/3205 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/417
CPC分类号： H01L29/41775 , H01L27/10808
摘要： A semiconductor device has MOS field effect transistors isolated by a field shield. The field shield has a gate of conductor layers formed spaced apart from each other on a silicon substrate through an insulating film and with the surface thereof being covered with an insulating film. In regions isolated by the field shield, MOS field effect transistors are formed. Each of the MOS field effect transistors has a gate electrode of a conductor layer formed on the silicon substrate through an insulating film and with the surface thereof being covered with an insulating film. An impurity diffused region is formed in a region on the silicon substrate between the gate electrode and the field shield. A portion on an exposed surface of the impurity diffused region between the field shield and the gate electrode is selectively filled with a tungsten buried layer. The tungsten buried layer is formed, flattened relative to the gate electrode and the gate constituting the field shield.
摘要翻译：半导体器件具有通过场屏蔽隔离的MOS场效应晶体管。场屏蔽具有通过绝缘膜在硅衬底上彼此隔开形成的导体层的栅极，并且其表面被绝缘膜覆盖。在通过场屏蔽隔离的区域中，形成MOS场效应晶体管。每个MOS场效应晶体管具有通过绝缘膜形成在硅衬底上并且其表面被绝缘膜覆盖的导体层的栅电极。在栅电极和场屏蔽之间的硅衬底上的区域中形成杂质扩散区域。在场屏蔽和栅电极之间的杂质扩散区域的暴露表面上的一部分选择性地填充有钨掩埋层。形成钨掩埋层，相对于构成场屏蔽体的栅电极和栅极变平。

8. 发明授权

US5180683A Method of manufacturing stacked capacitor type semiconductor memory device 失效
标题翻译：叠层电容器型半导体存储器件的制造方法
公开(公告)号：US5180683A
公开(公告)日：1993-01-19
申请号：US727781
申请日：1991-07-10
申请人： Wataru Wakamiya , Yoshinori Tanaka , Takahisa Eimori , Hiroji Ozaki , Hiroshi Kimura , Shinichi Satoh
发明人： Wataru Wakamiya , Yoshinori Tanaka , Takahisa Eimori , Hiroji Ozaki , Hiroshi Kimura , Shinichi Satoh
IPC分类号： H01L27/108
CPC分类号： H01L27/10817
摘要： A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor had various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.
摘要翻译：根据本发明的半导体存储器件包括具有一个晶体管和一个堆叠电容器的存储单元。堆叠的电容器堆叠在半导体衬底的表面上。此外，层叠电容器具有通过绝缘层在栅电极和字线上延伸的结构。电容器的下电极层具有各种凹凸形状，即台阶部分和形成在其表面上的突出部分。这些形状通过采用各种蚀刻工艺制成。下电极层在其上形成有各种凹凸形状，从而能够提高电容器的表面积和电容。

9. 发明授权

US5177571A LDD MOSFET with particularly shaped gate electrode immune to hot electron effect 失效
标题翻译：具有特殊形状的栅极电极的LDD MOSFET免疫电子效应
公开(公告)号：US5177571A
公开(公告)日：1993-01-05
申请号：US425017
申请日：1989-10-23
申请人： Shinichi Satoh , Wataru Wakamiya , Takahisa Eimori , Hiroji Ozaki , Yoshinori Tanaka
发明人： Shinichi Satoh , Wataru Wakamiya , Takahisa Eimori , Hiroji Ozaki , Yoshinori Tanaka
IPC分类号： H01L21/265 , H01L21/336 , H01L29/423 , H01L29/78
CPC分类号： H01L29/6659 , H01L29/42376 , H01L29/7836
摘要： Disclosed is an LDDMOSFET, in which a gate electrode (2) having a cross-sectional shape having a lower side and an upper side longer than the upper side is formed of only conductive materials, and diffusion layers (5b, 6b) of low concentration and high concentration constituting a drain are both formed so as to be overlapped with portions below the gate electrode (2) utilizing the shape of this gate electrode (2). Since the gate electrode (2) is formed of only the conductive materials, it becomes easy to word the gate electrode (2) so as to be in a desired shape. Since the diffusion layers (5b, 6b) of low concentration and high concentration constituting the drain are both overlapped with the portions below the gate electrode (2), the performance as a transistor is not degraded even if the polarity of the surface of the diffusion layer (5b, 6b) of low concentration is inverted by the effect of hot electrons.
摘要翻译：公开了一种LDDMOSFET，其中具有仅具有导电材料的具有下侧且上侧比上侧更长的截面形状的栅电极（2）和低浓度的扩散层（5b，6b）并且构成漏极的高浓度都利用该栅电极（2）的形状形成为与栅电极（2）下方的部分重叠。由于栅电极（2）仅由导电材料形成，容易使栅电极（2）成为期望的形状。由于构成漏极的低浓度和高浓度的扩散层（5b，6b）都与栅电极（2）下方的部分重叠，因此即使扩散表面的极性，晶体管的性能也不会降低低浓度的层（5b，6b）由热电子的作用而反转。

10. 发明授权

US5459344A Stacked capacitor type semiconductor memory device and manufacturing method thereof 失效
标题翻译：叠层电容器型半导体存储器件及其制造方法
公开(公告)号：US5459344A
公开(公告)日：1995-10-17
申请号：US727783
申请日：1991-07-10
申请人： Wataru Wakamiya , Yoshinori Tanaka , Takahisa Eimori , Hiroji Ozaki , Hiroshi Kimura , Shinichi Satoh
发明人： Wataru Wakamiya , Yoshinori Tanaka , Takahisa Eimori , Hiroji Ozaki , Hiroshi Kimura , Shinichi Satoh
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/02 , H01L27/10 , H01L27/108 , H01L29/68 , H01L29/78 , H01L29/92
CPC分类号： H01L27/10817
摘要： A semiconductor memory device according to the present invention comprises a memory cell having one transistor and one stacked capacitor. The stacked capacitor is stacked on the surface of a semiconductor substrate. Further, the stacked capacitor has a structure extending on a gate electrode and a word line through an insulating layer. A lower electrode layer of the capacitor has various concave/convex shapes, i.e. step portions and projecting portions formed on the surface thereof. These shapes are made by employing various etching processes. The lower electrode layer has such various concave/convex shapes formed thereon, so that a surface area and capacitance of the capacitor can be increased.
摘要翻译：根据本发明的半导体存储器件包括具有一个晶体管和一个堆叠电容器的存储单元。堆叠的电容器堆叠在半导体衬底的表面上。此外，层叠电容器具有通过绝缘层在栅电极和字线上延伸的结构。电容器的下电极层具有各种凹凸形状，即台阶部分和形成在其表面上的突出部分。这些形状通过采用各种蚀刻工艺制成。下电极层在其上形成有各种凹凸形状，从而能够提高电容器的表面积和电容。

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