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1. 发明申请

US20170365616A1 VERTICAL NON-VOLATILE MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME 审中-公开
公开(公告)号：US20170365616A1
公开(公告)日：2017-12-21
申请号：US15485579
申请日：2017-04-12
申请人： Shin-hwan KANG , Heon-kyu LEE , Kohji KANAMORI , Jae-duk LEE , Jae-hoon JANG , Kwang-soo KIM
发明人： Shin-hwan KANG , Heon-kyu LEE , Kohji KANAMORI , Jae-duk LEE , Jae-hoon JANG , Kwang-soo KIM
IPC分类号： H01L27/11582 , H01L29/04 , H01L27/1157 , H01L27/11524 , H01L21/768 , H01L23/532 , H01L23/528 , H01L23/522 , H01L29/16 , H01L27/11556
CPC分类号： H01L27/11582 , H01L21/76816 , H01L21/76877 , H01L23/5226 , H01L23/528 , H01L23/53271 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11573 , H01L29/04 , H01L29/16
摘要： A vertical non-volatile memory device includes a substrate including a cell region; a lower insulating layer on the substrate; a lower wiring pattern in the cell region having a predetermined pattern and connected to the substrate through the lower insulating layer; and a plurality of vertical channel layers extending in a vertical direction with respect to a top surface of the substrate in the cell region, spaced apart from one another in a horizontal direction with respect to the top surface of the substrate, and electrically connected to the lower wiring pattern. The memory device also includes a plurality of gate electrodes stacked alternately with interlayer insulating layers in the cell region in the vertical direction along a side wall of a vertical channel layer and formed to extend in a first direction along the horizontal direction.

2. 发明申请

US20170358590A1 INTEGRATED CIRCUIT DEVICE INCLUDING VERTICAL MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20170358590A1
公开(公告)日：2017-12-14
申请号：US15345763
申请日：2016-11-08
申请人： Shin-hwan KANG , Young-hwan SON , Dong-seog EUN , Chang-sup LEE , Jae-hoon JANG
发明人： Shin-hwan KANG , Young-hwan SON , Dong-seog EUN , Chang-sup LEE , Jae-hoon JANG
IPC分类号： H01L27/11556 , H01L27/11524 , H01L27/11582 , H01L27/1157
CPC分类号： H01L27/11556 , H01L27/11524 , H01L27/1157 , H01L27/11575 , H01L27/11582
摘要： In one embodiment, the semiconductor device includes a stack of alternating interlayer insulating layers and conductive layers on a substrate. Each of the conductive layers extends in a first direction less than a previous one of the conductive layers to define a landing portion of the previous one of the conductive layers. An insulating plug is in one of the conductive layers under one of the landing portions, and a contact plug extends from an upper surface of the one of the landing portions.

3. 发明申请

US20100046304A1 NON-VOLATILE MEMORY DEVICE AND ERASE METHOD 有权
标题翻译：非易失性存储器件和擦除方法
公开(公告)号：US20100046304A1
公开(公告)日：2010-02-25
申请号：US12539829
申请日：2009-08-12
申请人： Jae-hun JEONG , Soon-moon JUNG , Han-soo KIM , Jae-hoon JANG
发明人： Jae-hun JEONG , Soon-moon JUNG , Han-soo KIM , Jae-hoon JANG
IPC分类号： G11C16/16 , G11C16/04 , G11C11/34
CPC分类号： G11C16/16 , G11C16/0483
摘要： Provided is a non-volatile memory device including first and second, vertically stacked semiconductor substrates, a plurality of non-volatile memory cell transistors formed in a row on the first and second semiconductor substrates, and a plurality of word lines connected to gates of the plurality of non-volatile memory cell transistors. The plurality of non-volatile memory cell transistors are grouped into two or more memory cell blocks, such that a first voltage is applied to the first semiconductor substrate including a first memory cell block to be erased, and either (1) a second voltage less than the first voltage and greater than 0V is applied to the second semiconductor substrate not including the first memory cell block, or (2) the second semiconductor substrate not including the first memory cell block is allowed to electrically float.
摘要翻译：提供了一种非易失性存储器件，包括第一和第二垂直堆叠的半导体衬底，在第一和第二半导体衬底上形成为一行的多个非易失性存储单元晶体管，以及连接到第一和第二半导体衬底的栅极的多条字线多个非易失性存储单元晶体管。多个非易失性存储单元晶体管被分组成两个或更多个存储单元块，使得第一电压被施加到第一半导体衬底，该第一半导体衬底包括要擦除的第一存储单元块，以及（1）第二电压较小比不包括第一存储单元块的第二半导体衬底施加大于0V的第一电压，或者（2）不包括第一存储单元块的第二半导体衬底被电浮动。

4. 发明申请

US20100046294A1 NON-VOLATILE MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20100046294A1
公开(公告)日：2010-02-25
申请号：US12486924
申请日：2009-06-18
申请人： Jae-hun JEONG , Soon-moon JUNG , Han-soo KIM , Jae-hoon JANG
发明人： Jae-hun JEONG , Soon-moon JUNG , Han-soo KIM , Jae-hoon JANG
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/10 , G11C16/0483
摘要： A non-volatile memory device includes first and second strings memory cell transistors, related first and second word lines respectively connected to gates of the first string memory cell transistors, wherein respective first and second word lines are connected to commonly receive a bias voltage. The non-volatile memory device also includes dummy cell transistors connected to the first and second strings, and first and second dummy word lines configured to receive different bias voltages.
摘要翻译：非易失性存储器件包括分别连接到第一串存储单元晶体管的栅极的第一和第二串存储单元晶体管，相关的第一和第二字线，其中相应的第一和第二字线被连接以共同接收偏置电压。非易失性存储器件还包括连接到第一和第二串的虚拟单元晶体管，以及被配置为接收不同偏置电压的第一和第二虚拟字线。

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