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1. 发明授权

US08854817B2 Electronic device having fixing member 有权
标题翻译：具有固定构件的电子装置
公开(公告)号：US08854817B2
公开(公告)日：2014-10-07
申请号：US13570279
申请日：2012-08-09
申请人： Shih-Yao Li , Jui-Wen Hung , Wei-Jen Huang
发明人： Shih-Yao Li , Jui-Wen Hung , Wei-Jen Huang
IPC分类号： H05K7/20 , F28D15/00
CPC分类号： H01L23/467 , H01L23/3672 , H01L23/4006 , H01L23/427 , H01L2924/0002 , H01L2924/00
摘要： An exemplary electronic device includes an electronic component, a heat dissipation device, a fixing member and a casing contained the electronic component, the heat dissipation device and the fixing member therein. The heat dissipation device thermally contacts the electronic component. The fixing member includes a main body and an engaging portion extending from the main body. The engaging portion fixes the heat dissipation device to the fixing member. Fasteners extend through the casing and engage the main body of the fixing member to secure the fixing member on the casing.
摘要翻译：示例性的电子设备包括电子部件，散热装置，固定部件和容纳电子部件，散热装置和固定部件的壳体。散热装置与电子部件热接触。固定构件包括主体和从主体延伸的接合部。接合部将散热装置固定在固定部件上。紧固件延伸穿过壳体并接合固定构件的主体以将固定构件固定在壳体上。

2. 发明授权

US08657471B2 LED lamp 失效
标题翻译：点灯
公开(公告)号：US08657471B2
公开(公告)日：2014-02-25
申请号：US13169039
申请日：2011-06-27
申请人： Wei-Jen Huang , Jui-Wen Hung , Ching-Bai Hwang
发明人： Wei-Jen Huang , Jui-Wen Hung , Ching-Bai Hwang
IPC分类号： F21V29/00
CPC分类号： F21V29/51 , F21K9/232 , F21V3/00 , F21V29/006 , F21V29/773 , F21Y2115/10
摘要： An LED lamp includes a heat sink, a heat pipe and an LED. The heat sink includes a connecting core and fins mounted around the connecting core. Each of the fins includes a plate-shaped main body and a flange extending perpendicularly from a periphery side of the main body. The flanges of the fins cooperatively form an annular planar top surface of the heat sink. The heat pipe includes a condensing section, an evaporating section parallel to and higher than the condensing section and an adiabatic section connected between the condensing section and the evaporating section. The condensing section is fixed to and thermally connects with the top surface of the heat sink. The LED is directly mounted on the evaporating section with a light emitting surface thereof facing outwardly.
摘要翻译： LED灯包括散热器，热管和LED。散热器包括连接芯和围绕连接芯安装的散热片。每个翅片包括板状主体和从主体的周边垂直延伸的凸缘。翅片的凸缘协同地形成散热器的环形平面顶表面。热管包括冷凝部，与冷凝部平行且高于冷凝部的蒸发部，以及连接在冷凝部和蒸发部之间的绝热部。冷凝部分与散热片的顶面固定并热连接。 LED直接安装在蒸发部分上，其发光表面面向外。

3. 发明授权

US10295301B2 Differential pressure type inflating device 有权
公开(公告)号：US10295301B2
公开(公告)日：2019-05-21
申请号：US15384295
申请日：2016-12-19
申请人： Yu-Wen Lin , Wei-Jen Huang , Tire Service Equipment Mfg., Inc.
发明人： Yu-Wen Lin , Wei-Jen Huang
IPC分类号： F16K15/20 , F41B11/60 , F16K31/363 , F41B11/72 , F16K15/18 , F16K15/02 , F16K31/122
摘要： A differential pressure type inflating device, adapted for fast inflating the devices that need inflating, comprises a gas container, a relief valve, a gas nozzle, a pipe joint, a switch valve, and a relief pipe. When external high pressure gas enters the gas container and renders the gas pressures in the gas container and the relief pipe reaching a balance condition, the switch valve can be pressed to generate pressure drop in the relief pipe, which launches the relief valve and discharges the high pressure gas in the gas container from the gas nozzle. In this design, the gas container, relief valve, gas nozzle, relief pipe, and pipe joint are connected with screwing structures, so as to achieve the function of easy assembling.

4. 发明授权

US08107499B2 Speed negotiation for multi-speed communication devices 有权
标题翻译：多速通信设备的速度协商
公开(公告)号：US08107499B2
公开(公告)日：2012-01-31
申请号：US11821251
申请日：2007-06-21
申请人： Wei-Jen Huang , Chih-Tsung Huang , Claudio DeSanti
发明人： Wei-Jen Huang , Chih-Tsung Huang , Claudio DeSanti
IPC分类号： H04L3/06
CPC分类号： H04L5/1438
摘要： A method includes defining a pattern of time intervals, each time interval having a respective assigned communication speed, which alternates among multiple communication speeds supported by a first communication device. Synchronization requests are transmitted over a communication medium from the first communication device to a second communication device at the respective communication speed that is assigned in each interval in accordance with the pattern. While transmitting the synchronization requests, synchronization replies sent over the communication medium in response to the synchronization requests are received only at the respective communication speed that is assigned in each interval. Responsively to receiving the synchronization replies from the second communication device, one or more common communication speeds that are supported by both the first and the second communication devices are identified. Communication is established between the first and second communication devices over the communication medium using one of the common communication speeds.
摘要翻译：一种方法包括定义时间间隔的模式，每个时间间隔具有各自分配的通信速度，其在由第一通信设备支持的多个通信速度之间交替。同步请求通过通信介质从第一通信设备以按照该模式在每个间隔中分配的相应通信速度被发送到第二通信设备。在发送同步请求的同时，响应于同步请求通过通信介质发送的同步回复仅在每个间隔中分配的相应通信速度下被接收。响应于从第二通信设备接收同步响应，识别由第一和第二通信设备支持的一个或多个通用通信速度。使用公共通信速度之一，通过通信介质在第一和第二通信设备之间建立通信。

5. 发明授权

US06989689B2 Interconnection and input/output resources for programmable logic integrated circuit devices 失效
公开(公告)号：US06989689B2
公开(公告)日：2006-01-24
申请号：US10852858
申请日：2004-05-24
申请人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
发明人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
IPC分类号： H03K19/177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17792
摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.

6. 发明授权

US06894533B2 Interconnection and input/output resources for programmable logic integrated circuit devices 有权
标题翻译：可编程逻辑集成电路器件的互连和输入/输出资源
公开(公告)号：US06894533B2
公开(公告)日：2005-05-17
申请号：US10458431
申请日：2003-06-09
申请人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
发明人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
IPC分类号： G06F7/50 , G06F7/506 , H03K19/173 , H03K19/177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17792
摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.
摘要翻译：可编程逻辑集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间，从区域和/或区域之间进行可编程互连。这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。例如，这种双形互连资源的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分可具有明显更快的信号速度。辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

7. 发明授权

US06366120B1 Interconnection resources for programmable logic integrated circuit devices 有权
标题翻译：可编程逻辑集成电路器件的互连资源
公开(公告)号：US06366120B1
公开(公告)日：2002-04-02
申请号：US09517146
申请日：2000-03-02
申请人： James Schleicher , James Park , Sergey Shumarayev , Bruce Pedersen , Tony Ngai , Wei-Jen Huang , Victor Maruri , Rakesh Patel
发明人： James Schleicher , James Park , Sergey Shumarayev , Bruce Pedersen , Tony Ngai , Wei-Jen Huang , Victor Maruri , Rakesh Patel
IPC分类号： H03K190177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/17728 , H03K19/17736 , H03K19/17744 , H03K19/17792
摘要： A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.
摘要翻译：可编程逻辑器件具有许多可编程逻辑区域，以及可用于在几乎任何逻辑区域之间进行互连的相对通用的，可编程的互连资源。此外，各种类型的更多本地互连资源与每个逻辑区域相关联，以便于在相邻或附近的逻辑区域之间建立互连，而不需要使用这些互连的通用互连资源。本地互连资源通过相对直接的和因此的高速互连来支持逻辑区域的灵活聚集，优选地在逻辑区域的典型二维阵列中的水平和垂直方向。由本地互连资源提供的逻辑区域聚类选项优选地在逻辑区域阵列内是无边界的或基本无边界的。

8. 发明申请

US20090289660A1 INTERCONNECTION AND INPUT/OUTPUT RESOURCES FOR PROGRAMMABLE LOGIC INTEGRATED CIRCUIT DEVICES 有权
标题翻译：用于可编程逻辑集成电路设备的互连和输入/输出资源
公开(公告)号：US20090289660A1
公开(公告)日：2009-11-26
申请号：US12356317
申请日：2009-01-20
申请人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
发明人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter J. Kazarian , Andrew Leaver , David W. Mendel , Jim Park
IPC分类号： H03K19/177 , H03K19/173
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17792
摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.
摘要翻译：可编程逻辑集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间，从区域和/或区域之间进行可编程互连。这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。例如，这种双形互连资源的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分可具有明显更快的信号速度。辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

9. 发明申请

US20080317069A1 Speed negotiation for multi-speed communication devices 有权
标题翻译：多速通信设备的速度协商
公开(公告)号：US20080317069A1
公开(公告)日：2008-12-25
申请号：US11821251
申请日：2007-06-21
申请人： Wei-Jen Huang , Chih-Tsung Huang , Claudio DeSanti
发明人： Wei-Jen Huang , Chih-Tsung Huang , Claudio DeSanti
IPC分类号： H04J3/06
CPC分类号： H04L5/1438
摘要： A method includes defining a pattern of time intervals, each time interval having a respective assigned communication speed, which alternates among multiple communication speeds supported by a first communication device. Synchronization requests are transmitted over a communication medium from the first communication device to a second communication device at the respective communication speed that is assigned in each interval in accordance with the pattern. While transmitting the synchronization requests, synchronization replies sent over the communication medium in response to the synchronization requests are received only at the respective communication speed that is assigned in each interval. Responsively to receiving the synchronization replies from the second communication device, one or more common communication speeds that are supported by both the first and the second communication devices are identified. Communication is established between the first and second communication devices over the communication medium using one of the common communication speeds.
摘要翻译：一种方法包括定义时间间隔的模式，每个时间间隔具有各自分配的通信速度，其在由第一通信设备支持的多个通信速度之间交替。同步请求通过通信介质从第一通信设备以按照该模式在每个间隔中分配的相应通信速度被发送到第二通信设备。在发送同步请求的同时，响应于同步请求通过通信介质发送的同步回复仅在每个间隔中分配的相应通信速度下被接收。响应于从第二通信设备接收同步响应，识别由第一和第二通信设备支持的一个或多个通用通信速度。使用公共通信速度之一，通过通信介质在第一和第二通信设备之间建立通信。

10. 发明申请

US20080074143A1 Interconnection and input/output resources for programmable logic integrated circuit devices 有权
标题翻译：可编程逻辑集成电路器件的互连和输入/输出资源
公开(公告)号：US20080074143A1
公开(公告)日：2008-03-27
申请号：US11888317
申请日：2007-07-30
申请人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter Kazarian , Andrew Leaver , David Mendel , Jim Park
发明人： Tony Ngai , Bruce Pedersen , Sergey Shumarayev , James Schleicher , Wei-Jen Huang , Michael Hutton , Victor Maruri , Rakesh Patel , Peter Kazarian , Andrew Leaver , David Mendel , Jim Park
IPC分类号： H03K19/177
CPC分类号： G06F7/506 , H03K19/1737 , H03K19/177 , H03K19/17728 , H03K19/17736 , H03K19/1774 , H03K19/17744 , H03K19/17792
摘要： A programmable logic integrated circuit device has a plurality of regions of programmable logic disposed on the device in a plurality of intersecting rows and columns of such regions. Interconnection resources (e.g., interconnection conductors, signal buffers/drivers, programmable connectors, etc.) are provided on the device for making programmable interconnections to, from, and/or between the regions. At least some of these interconnection resources are provided in two forms that are architecturally similar (e.g., with similar and substantially parallel routing) but that have significantly different signal propagation speed characteristics. For example, a major or larger portion of such dual-form interconnection resources may have what may be termed normal signal speed, while a smaller minor portion may have significantly faster signal speed. Secondary (e.g., clock and clear) signal distribution may also be enhanced, and so may be input/output circuitry and cascade connections between adjacent or nearby logic modules on the device.
摘要翻译：可编程逻辑集成电路器件具有多个可编程逻辑区域，该多个可编程逻辑区域设置在该区域的多个相交行和列中的该器件上。在设备上提供互连资源（例如，互连导体，信号缓冲器/驱动器，可编程连接器等），用于对区域之间，从区域和/或区域之间进行可编程互连。这些互连资源中的至少一些以架构上相似的两种形式提供（例如，具有相似和基本上并行的路由），但具有显着不同的信号传播速度特性。例如，这种双形互连资源的主要或更大部分可以具有所谓的正常信号速度，而较小次要部分可具有明显更快的信号速度。辅助（例如时钟和清除）信号分布也可以被增强，并且因此也可以是设备上的相邻或附近逻辑模块之间的输入/输出电路和级联连接。

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