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1. 发明申请

US20130264719A1 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20130264719A1
公开(公告)日：2013-10-10
申请号：US13443496
申请日：2012-04-10
申请人： Shih-Hung Chen , Kuang-Yeu Hsieh , Cheng-Yuan Wang
发明人： Shih-Hung Chen , Kuang-Yeu Hsieh , Cheng-Yuan Wang
IPC分类号： H01L23/522 , H01L21/50
CPC分类号： H01L23/522 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L27/0203 , H01L27/1052 , H01L2224/0401 , H01L2224/04042 , H01L2224/06177 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/73207 , H01L2225/06513 , H01L2225/06541 , H01L2225/06568 , H01L2924/1431 , H01L2924/1435 , H01L2924/1443
摘要： A semiconductor structure includes first and second chips assembled to each other. The first chip includes N of first conductive lines, M of second conductive lines disposed on the first conductive lines, N of third conductive lines perpendicularly on the second conductive lines and parallel to the first conductive lines, N of first vias connected to the first conductive lines, M sets of second vias connected to the second conductive lines, and N sets of third vias connected to the third conductive lines. The second and first conductive lines form an overlapping area. The third conductive lines and N sets of the third vias include at least two groups respectively disposed in a first and a third regions of the overlapping area. M sets of second vias include at least two groups respectively disposed in a second region and a fourth region of the overlapping area.
摘要翻译：半导体结构包括彼此组装的第一和第二芯片。第一芯片包括N个第一导线，M个第二导线设置在第一导线上，N个第三导线垂直于第二导线并平行于第一导线，N个第一导通孔连接到第一导电线，连接到第二导线的M组第二通孔，以及连接到第三导线的N组第三通孔。第二和第一导电线形成重叠区域。第三导线和N组第三通孔包括分别设置在重叠区域的第一和第三区域中的至少两个组。 M组第二通孔包括分别设置在重叠区域的第二区域和第四区域中的至少两个组。

2. 发明授权

US08987787B2 Semiconductor structure and method for manufacturing the same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08987787B2
公开(公告)日：2015-03-24
申请号：US13443496
申请日：2012-04-10
申请人： Shih-Hung Chen , Kuang-Yeu Hsieh , Cheng-Yuan Wang
发明人： Shih-Hung Chen , Kuang-Yeu Hsieh , Cheng-Yuan Wang
IPC分类号： H01L27/118 , H01L23/52 , H01L23/34 , H01L23/48 , H01L29/40 , H01L21/00 , H01L21/336 , H01L21/3205 , H01L23/522 , H01L23/00 , H01L25/065 , H01L25/18 , H01L27/105 , H01L27/02
CPC分类号： H01L23/522 , H01L24/06 , H01L24/13 , H01L24/16 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L27/0203 , H01L27/1052 , H01L2224/0401 , H01L2224/04042 , H01L2224/06177 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16145 , H01L2224/73207 , H01L2225/06513 , H01L2225/06541 , H01L2225/06568 , H01L2924/1431 , H01L2924/1435 , H01L2924/1443
摘要： A semiconductor structure includes first and second chips assembled to each other. The first chip includes N of first conductive lines, M of second conductive lines disposed on the first conductive lines, N of third conductive lines perpendicularly on the second conductive lines and parallel to the first conductive lines, N of first vias connected to the first conductive lines, M sets of second vias connected to the second conductive lines, and N sets of third vias connected to the third conductive lines. The second and first conductive lines form an overlapping area. The third conductive lines and N sets of the third vias include at least two groups respectively disposed in a first and a third regions of the overlapping area. M sets of second vias include at least two groups respectively disposed in a second region and a fourth region of the overlapping area.
摘要翻译：半导体结构包括彼此组装的第一和第二芯片。第一芯片包括N个第一导线，M个第二导线设置在第一导线上，N个第三导线垂直于第二导线并平行于第一导线，N个第一导通孔连接到第一导电线，连接到第二导线的M组第二通孔，以及连接到第三导线的N组第三通孔。第二和第一导电线形成重叠区域。第三导线和N组第三通孔包括分别设置在重叠区域的第一和第三区域中的至少两个组。 M组第二通孔包括分别设置在重叠区域的第二区域和第四区域中的至少两个组。

3. 发明申请

US20060256626A1 Integrated Circuit with Analog or Multilevel Storage Cells and User-Selectable Sampling Frequency 有权
标题翻译：具有模拟或多电平存储单元的集成电路和用户可选择的采样频率
公开(公告)号：US20060256626A1
公开(公告)日：2006-11-16
申请号：US11460325
申请日：2006-07-27
申请人： Carl Werner , Andreas Haeberli , Leon Wong , Cheng-Yuan Wang , Hock So , Sau Wong
发明人： Carl Werner , Andreas Haeberli , Leon Wong , Cheng-Yuan Wang , Hock So , Sau Wong
IPC分类号： G11C7/10
CPC分类号： G11C11/5642 , G11C5/145 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C16/12 , G11C16/30 , G11C16/32 , G11C27/005 , G11C27/02 , G11C27/026
摘要： Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells (416) capable of multilevel or analog voltage level storage. The integrated circuit may store or record information in analog or digital form, or both. Information is stored in and retrieved from the integrated circuit using a user-selected sampling frequency. The user's selection of the sampling frequency is stored within the integrated circuit.
摘要翻译：技术用于在诸如集成电路的存储器单元的介质中存储信息，并且还从介质检索信息。集成电路包括能够进行多电平或模拟电压电平存储的非易失性存储单元（416）。集成电路可以以模拟或数字形式或两者存储或记录信息。使用用户选择的采样频率将信息存储在集成电路中并从集成电路检索。用户对采样频率的选择存储在集成电路内。

4. 发明申请

US20130326148A1 BUCKET-BASED WEAR LEVELING METHOD AND APPARATUS 有权
标题翻译：基于BUCKET的磨损水平方法和装置
公开(公告)号：US20130326148A1
公开(公告)日：2013-12-05
申请号：US13646426
申请日：2012-10-05
申请人： Po-Chao Fang , Cheng-Yuan Wang , Hsiang-Pang Li , Chi-Hao Chen , Pi-Cheng Hsiu , Tei-Wei Kuo
发明人： Po-Chao Fang , Cheng-Yuan Wang , Hsiang-Pang Li , Chi-Hao Chen , Pi-Cheng Hsiu , Tei-Wei Kuo
IPC分类号： G06F12/12
CPC分类号： G06F12/0246 , G06F12/1009 , G06F2212/7211
摘要： A method for memory management is provided for a memory including a plurality of pages. The method comprises assigning in-use pages to in-use buckets according to use counts. The in-use buckets include a low in-use bucket for a lowest range of use counts, and a high in-use bucket for a highest range of use counts. The method comprises assigning free pages to free buckets according to use counts. The free buckets include a low free bucket for a lowest range of use counts, and a high free bucket for a highest range of use counts. The method maintains use counts for in-use pages. On a triggering event for a current in-use page, the method determines whether the use count of the current in-use page exceeds a hot swap threshold, and if so moves data in the current in-use page to a lead page in the low free bucket.
摘要翻译：为包括多页的存储器提供存储器管理方法。该方法包括根据使用次数将使用中的页面分配给使用中的桶。使用中的铲斗包括用于最低使用数量的低使用桶，以及用于最高使用范围的高使用桶。该方法包括根据使用次数将免费页面分配给空闲桶。免费的铲斗包括一个低的免费铲斗，用于最低使用范围，以及一个高免费的铲斗，用于最高使用范围。该方法维护使用中页面的使用计数。在当前使用中页面的触发事件中，该方法确定当前使用中页面的使用次数是否超过热插拔阈值，如果是，则将当前使用中的页面中的数据移动到低免费桶。

5. 发明授权

US08769189B2 Method and apparatus for byte-access in block-based flash memory 有权
标题翻译：基于块的闪存中的字节访问的方法和装置
公开(公告)号：US08769189B2
公开(公告)日：2014-07-01
申请号：US12768368
申请日：2010-04-27
申请人： Hsiang-Pang Li , Chung-Jae Doong , Cheng-Yuan Wang
发明人： Hsiang-Pang Li , Chung-Jae Doong , Cheng-Yuan Wang
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7202 , G06F2212/7207
摘要： Techniques are described herein for managing data in a block-based flash memory device which avoid the need to perform sector erase operations each time data stored in the flash memory device is updated. As a result, a large number of write operations can be performed before a sector erase operation is needed. In addition, the block-based flash memory can emulate both programming and erasing on a byte-by-byte basis, like that provided by an EEPROM.
摘要翻译：这里描述了用于管理基于块的快闪存储器件中的数据的技术，其避免了每次更新存储在闪存器件中的数据时执行扇区擦除操作。结果，在需要扇区擦除操作之前可以执行大量写入操作。此外，基于块的闪存可以逐个字节地仿真编程和擦除，如EEPROM提供的那样。

6. 发明申请

US20100293320A1 METHOD AND APPARATUS FOR BYTE-ACCESS IN BLOCK-BASED FLASH MEMORY 有权
标题翻译：用于基于块的闪存中的字节访问的方法和装置
公开(公告)号：US20100293320A1
公开(公告)日：2010-11-18
申请号：US12768368
申请日：2010-04-27
申请人： Hsiang-Pang Li , Chung-Jae Doong , Cheng-Yuan Wang
发明人： Hsiang-Pang Li , Chung-Jae Doong , Cheng-Yuan Wang
IPC分类号： G06F12/00 , G06F12/02 , G06F12/08
CPC分类号： G06F12/0246 , G06F2212/7201 , G06F2212/7202 , G06F2212/7207
摘要： Techniques are described herein for managing data in a block-based flash memory device which avoid the need to perform sector erase operations each time data stored in the flash memory device is updated. As a result, a large number of write operations can be performed before a sector erase operation is needed. In addition, the block-based flash memory can emulate both programming and erasing on a byte-by-byte basis, like that provided by an EEPROM.
摘要翻译：这里描述了用于管理基于块的快闪存储器件中的数据的技术，其避免了每次更新存储在闪存器件中的数据时执行扇区擦除操作。结果，在需要扇区擦除操作之前可以执行大量写入操作。此外，基于块的闪存可以逐个字节地仿真编程和擦除，如EEPROM提供的那样。

7. 发明授权

US09251056B2 Bucket-based wear leveling method and apparatus 有权
标题翻译：基于铲斗的磨损均衡方法和装置
公开(公告)号：US09251056B2
公开(公告)日：2016-02-02
申请号：US13646426
申请日：2012-10-05
申请人： Po-Chao Fang , Cheng-Yuan Wang , Hsiang-Pang Li , Chi-Hao Chen , Pi-Cheng Hsiu , Tei-Wei Kuo
发明人： Po-Chao Fang , Cheng-Yuan Wang , Hsiang-Pang Li , Chi-Hao Chen , Pi-Cheng Hsiu , Tei-Wei Kuo
IPC分类号： G06F12/12 , G06F12/02 , G06F12/10
CPC分类号： G06F12/0246 , G06F12/1009 , G06F2212/7211
摘要： A method for memory management is provided for a memory including a plurality of pages. The method comprises assigning in-use pages to in-use buckets according to use counts. The in-use buckets include a low in-use bucket for a lowest range of use counts, and a high in-use bucket for a highest range of use counts. The method comprises assigning free pages to free buckets according to use counts. The free buckets include a low free bucket for a lowest range of use counts, and a high free bucket for a highest range of use counts. The method maintains use counts for in-use pages. On a triggering event for a current in-use page, the method determines whether the use count of the current in-use page exceeds a hot swap threshold, and if so moves data in the current in-use page to a lead page in the low free bucket.
摘要翻译：为包括多页的存储器提供存储器管理方法。该方法包括根据使用次数将使用中的页面分配给使用中的桶。使用中的铲斗包括用于最低使用数量的低使用桶，以及用于最高使用范围的高使用桶。该方法包括根据使用次数将免费页面分配给空闲桶。免费的铲斗包括一个低的免费铲斗，用于最低使用范围，以及一个高免费的铲斗，用于最高使用范围。该方法维护使用中页面的使用计数。在当前使用中页面的触发事件中，该方法确定当前使用中页面的使用次数是否超过热插拔阈值，如果是，则将当前使用中的页面中的数据移动到低免费桶。

8. 发明申请

US20080049498A1 Integrated Circuit with Analog or Multilevel Storage Cells and User-Selectable Sampling Frequency 有权
标题翻译：具有模拟或多电平存储单元的集成电路和用户可选择的采样频率
公开(公告)号：US20080049498A1
公开(公告)日：2008-02-28
申请号：US11876093
申请日：2007-10-22
申请人： Carl Werner , Andreas Haeberli , Leon Wong , Cheng-Yuan Wang , Hock So , Sau Wong
发明人： Carl Werner , Andreas Haeberli , Leon Wong , Cheng-Yuan Wang , Hock So , Sau Wong
IPC分类号： G11C7/16
CPC分类号： G11C11/5642 , G11C5/145 , G11C7/16 , G11C11/56 , G11C11/5621 , G11C11/5628 , G11C16/12 , G11C16/30 , G11C16/32 , G11C27/005 , G11C27/02 , G11C27/026
摘要： Techniques are used to store information in a medium such as the memory cells of an integrated circuit, and also retrieval of information from the medium. The integrated circuit includes nonvolatile memory cells (416) capable of multilevel or analog voltage level storage. The integrated circuit may store or record information in analog or digital form, or both. Information is stored in and retrieved from the integrated circuit using a user-selected sampling frequency. The user's selection of the sampling frequency is stored within the integrated circuit.
摘要翻译：技术用于在诸如集成电路的存储器单元的介质中存储信息，并且还从介质检索信息。集成电路包括能够进行多电平或模拟电压电平存储的非易失性存储单元（416）。集成电路可以以模拟或数字形式或两者存储或记录信息。使用用户选择的采样频率将信息存储在集成电路中并从集成电路检索。用户对采样频率的选择存储在集成电路内。

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