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1. 发明申请

US20090091032A1 Bond Pad Design for Fine Pitch Wire Bonding 有权
标题翻译：用于细间距线接合的焊盘设计
公开(公告)号：US20090091032A1
公开(公告)日：2009-04-09
申请号：US11868850
申请日：2007-10-08
申请人： Shih-Hsun Hsu , Hao-Yi Tsai , Benson Liu , Chia-Lun Tsai , Hsien-Wei Chen , Anbiarshy N.F. Wu , Shang-Yun Hou , Shin-Puu Jeng
发明人： Shih-Hsun Hsu , Hao-Yi Tsai , Benson Liu , Chia-Lun Tsai , Hsien-Wei Chen , Anbiarshy N.F. Wu , Shang-Yun Hou , Shin-Puu Jeng
IPC分类号： H01L23/48
CPC分类号： H01L24/06 , H01L22/32 , H01L24/05 , H01L2224/05552 , H01L2224/05599 , H01L2224/0603 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/01076 , H01L2924/01082
摘要： A bonding pad design is disclosed that includes one or more pad groups on a semiconductor device. Each pad group is made up of two or more bonding pads that have an alternating orientation, such that adjacent bonding pads have their bond ball on opposite sides in relation to the adjacent bonding pad.
摘要翻译：公开了一种焊盘设计，其包括半导体器件上的一个或多个焊盘组。每个焊盘组由具有交替取向的两个或更多个焊盘组成，使得相邻的焊盘相对于相邻的焊盘在相对的两侧具有焊接球。

2. 发明申请

US20080246031A1 PCM pad design for peeling prevention 审中-公开
标题翻译： PCM垫设计防脱皮
公开(公告)号：US20080246031A1
公开(公告)日：2008-10-09
申请号：US11784632
申请日：2007-04-09
申请人： Hao-Yi Tsai , Shih-Hsun Hsu , Hsien-Wei Chen , Benson Liu , Chia-Lun Tsai , Anbiarshy N.F. Wu
发明人： Hao-Yi Tsai , Shih-Hsun Hsu , Hsien-Wei Chen , Benson Liu , Chia-Lun Tsai , Anbiarshy N.F. Wu
IPC分类号： H01L23/544 , H01L21/66
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure is provided. The semiconductor structure includes a semiconductor chip and a scribe line adjoining the semiconductor chip. A conductive feature is formed in the scribe line and exposed on the surface of the scribe lines, wherein the conductive feature has an edge facing the semiconductor chip. A kerf path is in the scribe line. A first cut is formed in the conductive feature, wherein the first cut extends from the first edge to the kerf path.
摘要翻译：提供半导体结构。半导体结构包括半导体芯片和与半导体芯片相邻的划线。导电特征形成在划线中并暴露在划线的表面上，其中导电特征具有面向半导体芯片的边缘。切割路径在划线中。在导电特征中形成第一切口，其中第一切口从第一边缘延伸到切口路径。

3. 发明申请

US20090321890A1 Protective Seal Ring for Preventing Die-Saw Induced Stress 有权
标题翻译：用于防止模切诱发应力的保护密封圈
公开(公告)号：US20090321890A1
公开(公告)日：2009-12-31
申请号：US12347026
申请日：2008-12-31
申请人： Shin-Puu Jeng , Hsien-Wei Chen , Shang-Yun Hou , Hao-Yi Tsai , Anbiarshy N.F. Wu , Yu-Wen Liu
发明人： Shin-Puu Jeng , Hsien-Wei Chen , Shang-Yun Hou , Hao-Yi Tsai , Anbiarshy N.F. Wu , Yu-Wen Liu
IPC分类号： H01L23/10
CPC分类号： H01L21/78 , H01L23/562 , H01L23/564 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip includes a semiconductor substrate; a plurality of low-k dielectric layers over the semiconductor substrate; a first passivation layer over the plurality of low-k dielectric layers; and a second passivation layer over the first passivation layer. A first seal ring is adjacent to an edge of the semiconductor chip, wherein the first seal ring has an upper surface substantially level to a bottom surface of the first passivation layer. A second seal ring is adjacent to the first seal ring and on an inner side of the semiconductor chip than the first seal ring. The second seal ring includes a pad ring in the first passivation layer and the second passivation layer. A trench ring includes at least a portion directly over the first seal ring. The trench ring extends from a top surface of the second passivation layer down to at least an interface between the first passivation layer and the second passivation layer.
摘要翻译：半导体芯片包括半导体衬底; 半导体衬底上的多个低k电介质层; 在所述多个低k电介质层上的第一钝化层; 以及在所述第一钝化层上的第二钝化层。第一密封环邻近半导体芯片的边缘，其中第一密封环具有基本上平坦于第一钝化层的底表面的上表面。第二密封环与第一密封环相邻，并且在半导体芯片的内侧与第一密封环相邻。第二密封环包括在第一钝化层和第二钝化层中的焊盘环。沟槽环包括直接在第一密封环上的至少一部分。沟槽环从第二钝化层的顶表面延伸到至少第一钝化层和第二钝化层之间的界面。

4. 发明申请

US20090011539A1 Flexible Structures for Interconnect Reliability Test 有权
标题翻译：互连可靠性测试的灵活结构
公开(公告)号：US20090011539A1
公开(公告)日：2009-01-08
申请号：US11971072
申请日：2008-01-08
申请人： Shin-Puu Jeng , Shang-Yun Hou , Hao-Yi Tsai , Anbiarshy N.F. Wu
发明人： Shin-Puu Jeng , Shang-Yun Hou , Hao-Yi Tsai , Anbiarshy N.F. Wu
IPC分类号： H01L21/00
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an integrated circuit structure includes forming a test wafer. The step of forming the test wafer includes providing a first semiconductor substrate; and forming a first plurality of unit blocks over the first semiconductor substrate. Each of the first plurality of unit blocks includes a plurality of connection block cells arranged as an array. Each of the connection block cells includes two connection blocks, and a metal line connecting the two connection blocks. The method further includes forming a plurality of unit block boundary lines separating the first plurality of unit blocks from each other; and forming a first plurality of metal lines connecting a portion of the first plurality of unit blocks.
摘要翻译：一种用于形成集成电路结构的方法包括形成测试晶片。形成测试晶片的步骤包括提供第一半导体衬底; 以及在所述第一半导体衬底上形成第一多个单元块。第一多个单元块中的每一个包括被排列成阵列的多个连接块单元。每个连接块单元包括两个连接块和连接两个连接块的金属线。该方法还包括形成将第一多个单元块彼此分开的多个单位块边界线; 以及形成连接所述第一多个单元块的一部分的第一多个金属线。

5. 发明申请

US20080277659A1 Test structure for semiconductor chip 审中-公开
标题翻译：半导体芯片测试结构
公开(公告)号：US20080277659A1
公开(公告)日：2008-11-13
申请号：US11801529
申请日：2007-05-10
申请人： Shih-Hsun Hsu , Hsien-Wei Chen , Anbiarshy N.F. Wu
发明人： Shih-Hsun Hsu , Hsien-Wei Chen , Anbiarshy N.F. Wu
IPC分类号： H01L23/544
CPC分类号： H01L27/0203 , H01L22/34 , H01L23/585 , H01L2223/5446 , H01L2223/54493 , H01L2924/0002 , H01L2924/00
摘要： A test structure for use in a semiconductor chip. In a preferred embodiment, a number of die are formed in an array on a semiconductor wafer substrate. Each die includes an active area defined by a seal ring and is separated from those adjacent to it by a thin scribe line. In addition to the operational structures formed in the active area of each die, one or more test structures are formed. In a preferred embodiment, these test structures are formed into one or more PCM (process control monitor) test pattern layout areas that are positioned near the seal ring and outside of the operational bond pads. Some or all of individual pads in the PCM test pattern layout area may then be connected to corresponding features on adjacent dice, and in some applications enable the simultaneous performance of WAT (wafer acceptance test) and CP (circuit probe) testing.
摘要翻译：用于半导体芯片的测试结构。在优选实施例中，在半导体晶片衬底上以阵列形式形成多个管芯。每个模具包括由密封环限定的有效区域，并通过薄的划线与其相邻的区域分开。除了在每个管芯的有源区域中形成的操作结构之外，还形成一个或多个测试结构。在优选实施例中，这些测试结构被形成为位于密封环附近和操作接合焊盘外部的一个或多个PCM（过程控制监视器）测试图案布局区域。 PCM测试图案布局区域中的单个焊盘中的一些或全部可以连接到相邻裸片上的相应特征，并且在某些应用中，能够同时执行WAT（晶片验收测试）和CP（电路探针）测试。

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