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1. 发明授权

US08429332B2 Multi-channel hybrid density memory storage device and control method thereof 有权
公开(公告)号：US08429332B2
公开(公告)日：2013-04-23
申请号：US12382442
申请日：2009-03-17
申请人： Ming-Dar Chen , Chuan-Sheng Lin , Tso-Cheng Su , Shih-Fang Hung , Tzu-Wei Fang , Hsiang-An Hsieh
发明人： Ming-Dar Chen , Chuan-Sheng Lin , Tso-Cheng Su , Shih-Fang Hung , Tzu-Wei Fang , Hsiang-An Hsieh
IPC分类号： G06F13/00 , G06F13/28 , G06F11/00 , H03M13/00
CPC分类号： G06F12/0246 , G06F11/1048 , G06F2212/7208
摘要： The present invention discloses a control method of a multi-channel hybrid density memory storage device for access a user data. The storage device includes a plurality of low density memories (LDM) and high density memories (HDM). The steps of the method comprises: first, determining where the user data transmitted; then, using one of two error correction circuits which have different error correction capability to encode or decode the user data.

2. 发明申请

US20100082883A1 Hybrid density memory system and control method thereof 审中-公开
标题翻译：混合密度记忆系统及其控制方法
公开(公告)号：US20100082883A1
公开(公告)日：2010-04-01
申请号：US12379698
申请日：2009-02-26
申请人： Ming-Dar Chen , Tso-Cheng Su , Shih-Fang Hung , Tzu-Wei Fang , Hsiang-An Hsieh
发明人： Ming-Dar Chen , Tso-Cheng Su , Shih-Fang Hung , Tzu-Wei Fang , Hsiang-An Hsieh
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F2212/7202 , G11C2211/5641
摘要： A control method of a memory system for accessing an updated data between a host and the memory system is provided. The host has storage space which is divided into a plurality of logical segments to access the data. The system includes a high density memory and a low density memory, and the high density memory includes a plurality of physical segments to access the data. The control method includes the following steps: first, providing a LDM table in the memory system to indicate the allocation information of the low density memory; finally, deciding where the data is written to is according to its properties and the LDM table.
摘要翻译：提供了一种用于访问主机和存储器系统之间的更新数据的存储器系统的控制方法。主机具有被分成多个逻辑段以存取数据的存储空间。该系统包括高密度存储器和低密度存储器，并且高密度存储器包括用于访问数据的多个物理段。该控制方法包括以下步骤：首先，在存储器系统中提供LDM表以指示低密度存储器的分配信息; 最后，根据其属性和LDM表来决定数据写入的位置。

3. 发明申请

US20100318874A1 ELECTRONIC MEMORY DEVICE AND METHOD FOR ERROR CORRECTING THEREOF 审中-公开
标题翻译：电子存储器件及其错误校正方法
公开(公告)号：US20100318874A1
公开(公告)日：2010-12-16
申请号：US12649799
申请日：2009-12-30
申请人： Shih-Fang Hung , Tzu-Wei Fang , Hsiang-An Hsieh
发明人： Shih-Fang Hung , Tzu-Wei Fang , Hsiang-An Hsieh
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1068 , G11C2029/0411
摘要： An electronic memory device includes a controller and a memory unit. The controller includes a micro processor, a host interface, a memory unit interface connected to the memory unit, a data cache area for provisionally storing data, an ECC unit coupled to the memory unit for testing whether there is any error bit in the data or not, and an error correcting unit coupled to the memory unit. If an error bit in the data is found and can be dealt by the ECC unit, the error bit is then directly recovered by the ECC unit. However, if the error bit exceeds beyond the processing capability of the ECC unit, the error correcting unit is selected to primarily invert predetermined data bit till the number of the error can be successfully recovered by the ECC unit.
摘要翻译：电子存储装置包括控制器和存储器单元。控制器包括微处理器，主机接口，连接到存储器单元的存储器单元接口，用于临时存储数据的数据高速缓存区域，耦合到存储器单元的ECC单元，用于测试数据中是否存在任何错误位，或者以及耦合到存储器单元的纠错单元。如果发现数据中的错误位并且可以由ECC单元处理，则该错误位由ECC单元直接恢复。然而，如果错误位超出ECC单元的处理能力，则选择错误校正单元主要反转预定的数据位，直到ECC单元能够成功地恢复错误的数目。

4. 发明申请

US20090307418A1 Multi-channel hybrid density memory storage device and control method thereof 有权
标题翻译：多通道混合密度存储器及其控制方法
公开(公告)号：US20090307418A1
公开(公告)日：2009-12-10
申请号：US12382442
申请日：2009-03-17
申请人： Ming-Dar Chen , Chuan-Sheng Lin , Tso-Cheng Su , Shih-Fang Hung , Tzu-Wei Fang , Hsiang-An Hsieh
发明人： Ming-Dar Chen , Chuan-Sheng Lin , Tso-Cheng Su , Shih-Fang Hung , Tzu-Wei Fang , Hsiang-An Hsieh
IPC分类号： G06F12/06 , H03M13/09
CPC分类号： G06F12/0246 , G06F11/1048 , G06F2212/7208
摘要： The present invention discloses a control method of a multi-channel hybrid density memory storage device for access a user data. The storage device includes a plurality of low density memories (LDM) and high density memories (HDM). The steps of the method comprises: first, determining where the user data transmitted; then, using one of two error correction circuits which have different error correction capability to encode or decode the user data.
摘要翻译：本发明公开了一种用于访问用户数据的多通道混合密度存储装置的控制方法。存储装置包括多个低密度存储器（LDM）和高密度存储器（HDM）。该方法的步骤包括：首先确定用户数据发送的位置; 然后，使用具有不同纠错能力的两个纠错电路中的一个对用户数据进行编码或解码。

5. 发明申请

US20100332738A1 STORAGE DEVICE AND DATA PROCESSING METHOD 审中-公开
标题翻译：存储设备和数据处理方法
公开(公告)号：US20100332738A1
公开(公告)日：2010-12-30
申请号：US12785405
申请日：2010-05-21
申请人： Ming-Dar Chen , Chuan-Sheng Lin , Tzu-Wei Fang , Hsiang-An Hsieh
发明人： Ming-Dar Chen , Chuan-Sheng Lin , Tzu-Wei Fang , Hsiang-An Hsieh
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G11C16/349 , G11C16/04 , G11C29/08 , G11C2029/0401 , G11C2029/0409
摘要： A storage device for connecting to a host system includes a flash memory and a controller coupled to the flash memory. The flash memory includes a plurality of memory blocks. The controller writes test data to the flash memory, and compares the test data read from the flash memory with the original test data to generate a bit error message corresponding to the flash memory. Then, the controller chooses and labels a quick read block from the plurality of memory blocks according to the bit error message, and finally writes a specific file to the quick read block.
摘要翻译：用于连接到主机系统的存储设备包括闪存和耦合到闪速存储器的控制器。闪存包括多个存储块。控制器将测试数据写入闪速存储器，并将从闪存读取的测试数据与原始测试数据进行比较，以产生与闪存相对应的位错误消息。然后，控制器根据位错误消息从多个存储块中选择并标记快速读块，最后将特定文件写入快速读块。

6. 发明授权

US08307163B2 Hybrid density memory storage device 有权
标题翻译：混合密度存储器
公开(公告)号：US08307163B2
公开(公告)日：2012-11-06
申请号：US12050593
申请日：2008-03-18
申请人： Ming-Dar Chen , Chuan-Sheng Lin , Hui-Neng Chang , Hsiang-An Hsieh
发明人： Ming-Dar Chen , Chuan-Sheng Lin , Hui-Neng Chang , Hsiang-An Hsieh
IPC分类号： G06F12/00
CPC分类号： G06F12/0246 , G06F2212/1036 , G06F2212/7208 , G06F2212/7211 , G11C11/56 , G11C2211/5641
摘要： The present invention discloses a hybrid density memory storage device configured to store data responsive to a host and a file system thereof. The hybrid density memory storage device includes a non-volatile memory, a hot data buffer and a control unit. The non-volatile memory includes a high density storage space and a low density storage space. The control unit is coupled between the host, the non-volatile memory, and the hot data buffer. The control unit has a hot list used for recording a plurality of logical locations of hot data, and the control unit is capable of accessing data in/out the hot data buffer in accordance with the hot list.
摘要翻译：本发明公开了一种混合密度存储器存储装置，被配置为存储响应于主机及其文件系统的数据。混合密度存储器存储装置包括非易失性存储器，热数据缓冲器和控制单元。非易失性存储器包括高密度存储空间和低密度存储空间。控制单元耦合在主机，非易失性存储器和热数据缓冲器之间。控制单元具有用于记录热数据的多个逻辑位置的热列表，并且控制单元能够根据热列表访问/输出热数据缓冲器中的数据。

7. 发明授权

US08205036B2 Non-volatile memory and controlling method thereof 有权
标题翻译：非易失性存储器及其控制方法
公开(公告)号：US08205036B2
公开(公告)日：2012-06-19
申请号：US12509287
申请日：2009-07-24
申请人： Ming-Dar Chen , Hsiang-An Hsieh , Chuan-Sheng Lin
发明人： Ming-Dar Chen , Hsiang-An Hsieh , Chuan-Sheng Lin
IPC分类号： G06F12/00
CPC分类号： G11C16/349 , G06F12/0246 , G06F2212/7211 , G11C16/3495
摘要： A non-volatile memory of present invention includes a number of memory blocks and a static wear leveling device. The static wear leveling device includes a memory unit for storing the erase counts of the memory blocks and a controlling unit for getting the erase counts from the memory unit, and calculating the standard deviation based on the EC, and deciding the way of the static wear leveling cycle according to the standard deviation. The controlling unit deciding the way of the static wear leveling cycle include the steps of setting at least one predetermined threshold point and judging whether the standard deviation of the erase counts is smaller than the predetermined threshold point. If the standard deviation of the erase counts is smaller than the predetermined threshold point, the static wear leveling cycle starts for a first amount of cycles and moves the static data stored a first number of memory blocks. If the standard deviation of the erase counts is bigger than the predetermined threshold point, starts for a second amount of cycles and moves the static data stored a second number of memory blocks.
摘要翻译：本发明的非易失性存储器包括多个存储块和静态损耗均衡装置。静态损耗均衡装置包括用于存储存储块的擦除计数的存储单元和用于从存储单元获取擦除计数的控制单元，并且基于EC计算标准偏差，并且确定静态磨损的方式调平周期根据标准偏差。决定静态磨损均衡循环的方式的控制单元包括设置至少一个预定阈值点并判断擦除计数的标准偏差是否小于预定阈值点的步骤。如果擦除计数的标准偏差小于预定阈值点，则静态磨损均衡循环开始第一次循环，并且移动存储有第一数量的存储块的静态数据。如果擦除计数的标准偏差大于预定的阈值点，则开始第二个循环量并且移动存储有第二数量的存储器块的静态数据。

8. 发明申请

US20100312950A1 ELECTRONIC STORAGE DEVICE AND CONTROL METHOD THEREOF 有权
标题翻译：电子储存装置及其控制方法
公开(公告)号：US20100312950A1
公开(公告)日：2010-12-09
申请号：US12651096
申请日：2009-12-31
申请人： Hsiang-An Hsieh
发明人： Hsiang-An Hsieh
IPC分类号： G06F12/00 , G06F12/02 , G06F12/10
CPC分类号： G06F12/0246 , G06F3/0616 , G06F3/0659 , G06F3/0679 , G06F12/08 , G06F2212/7201 , G06F2212/7203
摘要： An electronic storage device (320) for connecting with a host system (100) includes a storage unit (360) including at least one memory segment which has at least one physical block, a memory unit (350) receiving access commands sent from the host system, and a control unit (340) connecting with said memory unit. Each of the access commands contains at least a logical address which corresponds to a physical block. The control unit determines the command execution order of the access commands according to adjacent extent of the physical blocks in said memory segment to which the logical addresses of said access commands correspond. A control method of the electronic storage device is also disclosed in the present invention.
摘要翻译：一种用于与主机系统（100）连接的电子存储设备（320）包括一个存储单元（360），该存储单元包括至少一个具有至少一个物理块的存储区段，存储单元（350）接收从主机发送的访问命令系统和与所述存储器单元连接的控制单元（340）。每个访问命令至少包含与物理块对应的逻辑地址。所述控制单元根据与所述访问命令的逻辑地址相对应的所述存储区段中的物理块的相邻范围来确定访问命令的命令执行顺序。本发明还公开了电子存储装置的控制方法。

9. 发明申请

US20090300273A1 Flash memory apparatus with automatic interface mode switching 有权
标题翻译：具有自动接口模式切换的闪存设备
公开(公告)号：US20090300273A1
公开(公告)日：2009-12-03
申请号：US12232771
申请日：2008-09-24
申请人： Ming-Dar Chen , Chuan-Sheng Lin , Hsiang-An Hsieh
发明人： Ming-Dar Chen , Chuan-Sheng Lin , Hsiang-An Hsieh
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G06F13/1694
摘要： A flash memory controller with automatic interface mode switching is applied to a flash memory apparatus with a plurality of flash memories and the controller contains: a memory interface, a microprocessor, and an interface mode controller. The microprocessor recognizes the supported interface mode of every flash memory connected with the memory interface in an initial setting process, and individually sets the corresponding interface mode setting value into the interface mode controller. Thus, when the flash memory apparatus is operating in a normal operation state, the interface mode controller can output the corresponding interface mode setting value according to the present enabled flash memory, and the memory interface can adjust and switch the interface mode according to the interface mode setting value outputted by the interface mode controller. Thereby, the present invention can achieve the purpose whereby the flash memory apparatus can speed up accessing and increase efficiency.
摘要翻译：具有自动接口模式切换的闪速存储器控制器被应用于具有多个闪速存储器的闪存装置，并且控制器包括：存储器接口，微处理器和接口模式控制器。微处理器在初始设置过程中识别与存储器接口连接的每个闪存的支持的接口模式，并将相应的接口模式设置值单独设置为接口模式控制器。因此，当闪存装置工作在正常工作状态时，接口模式控制器可根据当前使能的闪存输出相应的接口模式设置值，并且存储器接口可以根据接口调整和切换接口模式模式设定值由界面模式控制器输出。因此，本发明可以实现闪速存储装置可以加速访问并提高效率的目的。

10. 发明申请

US20060271590A1 Volume information analysis module and method thereof 审中-公开
标题翻译：卷信息分析模块及其方法
公开(公告)号：US20060271590A1
公开(公告)日：2006-11-30
申请号：US11498891
申请日：2006-08-04
申请人： Hsiang-An Hsieh
发明人： Hsiang-An Hsieh
IPC分类号： G06F7/00
CPC分类号： G11B20/00086 , G06F3/0605 , G06F3/0632 , G06F3/0676 , G11B20/10
摘要： A volume information analysis module reads a data by an interface unit. The volume information analysis module uses a compare unit to compare the data. After comparing the data, the compare unit outputs a signal, and then a count unit accumulates result of the comparing according to the signal. A control unit receives a setting signal from a micro process unit to control the interface unit, the compare unit and the count unit. Thereby using the volume information analysis module can accelerate analysis speed and reduce loading of the micro process unit.
摘要翻译：音量信息分析模块通过接口单元读取数据。卷信息分析模块使用比较单元比较数据。在比较数据之后，比较单元输出信号，然后计数单元根据信号累加比较结果。控制单元从微处理单元接收设置信号以控制接口单元，比较单元和计数单元。因此使用卷信息分析模块可以加快分析速度，减少微处理单元的负载。

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