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1. 发明授权

US5615334A Memory reflection system and method for reducing bus utilization and device idle time in the event of faults 失效
标题翻译：存储器反射系统和方法，用于在发生故障时降低总线利用率和设备空闲时间
公开(公告)号：US5615334A
公开(公告)日：1997-03-25
申请号：US321205
申请日：1994-10-07
申请人： Shih-Chieh Wang , Wei-Wen Chang , Lu-Ping Chen
发明人： Shih-Chieh Wang , Wei-Wen Chang , Lu-Ping Chen
IPC分类号： G06F12/08 , G06F11/00 , G06F12/00
CPC分类号： G06F12/0833
摘要： A memory reflection scheme is disclosed including a snarfing agent provided with efficient memory reflection circuitry for snarfing data. The memory reflection circuitry is for snarfing particular data written back from a write back agent to a memory subsystem agent. In response to unsuccessfully snarfing the particular data written back from the write back agent to the memory subsystem agent, the memory reflection circuitry issues a command to read the particular data from the memory subsystem agent. However, the memory reflection circuitry only issues such a command if the write back agent successfully writes back the particular data to the memory subsystem agent.
摘要翻译：公开了一种存储器反射方案，其包括具有用于斩波数据的有效存储器反射电路的汲取剂。存储器反射电路用于将从写回代理写回的特定数据扼杀到存储器子系统代理。响应于将从回写代理写回的特定数据成功地扼杀到存储器子系统代理，存储器反射电路发出从存储器子系统代理读取特定数据的命令。然而，如果回写代理成功地将特定数据写回存储器子系统代理，则存储器反射电路仅发出这样的命令。

2. 发明授权

US5799207A Non-blocking peripheral access architecture having a register configure to indicate a path selection for data transfer between a master, memory, and an I/O device 失效
标题翻译：具有寄存器的非阻塞外设访问体系结构，用于指示主机，存储器和I / O设备之间的数据传输的路径选择
公开(公告)号：US5799207A
公开(公告)日：1998-08-25
申请号：US413807
申请日：1995-03-28
申请人： Shih-Chieh Wang , Wei-Wen Chang , Zen-Dar Hsu
发明人： Shih-Chieh Wang , Wei-Wen Chang , Zen-Dar Hsu
IPC分类号： G06F13/40 , G06F13/00
CPC分类号： G06F13/4027
摘要： A computer system is disclosed which has a master, such as a processor, a memory, and I/O device, a first transfer path, which includes a bus, and a second transfer path, which includes a transfer interconnection. Transfers between the memory and the I/O device are effected via the first path while transfers between the processor and the I/O device are transferred via the second path. The disparate treatment between these two types of transfers reduces the likelihood that the transfer via the second path is delayed and thereby reduces the likelihood that the master is totally blocked from operation.
摘要翻译：公开了一种具有诸如处理器，存储器和I / O设备的主设备，包括总线的第一传送路径和包括传送互连的第二传送路径的计算机系统。存储器和I / O设备之间的传输通过第一路径实现，而处理器和I / O设备之间的传输通过第二路径传送。这两种类型的传输之间的不同处理降低了经由第二路径的传送被延迟的可能性，从而降低了主机被完全阻止操作的可能性。

3. 发明授权

US5623635A Memory consistent pre-ownership method and system for transferring data between and I/O device and a main memory 失效
标题翻译：内存一致的预拥有方法和用于在I / O设备和主存储器之间传输数据的系统
公开(公告)号：US5623635A
公开(公告)日：1997-04-22
申请号：US714888
申请日：1996-09-17
申请人： Chang-Lun Chen , Allen S. C. Wang , Wei-Wen Chang
发明人： Chang-Lun Chen , Allen S. C. Wang , Wei-Wen Chang
IPC分类号： G06F12/08 , G06F12/14 , G06F13/20
CPC分类号： G06F12/0835
摘要： A method and system is disclosed for efficiently transferring a sequence of data words from an I/O device to sequential addresses in a main memory via an I/O bridge. The sequence of data words to be transferred includes one or more subsequences of data words. Each subsequence of data words include only data words destined to addresses of the main memory in which data words of only one data line are stored. The I/O bridge has control logic for receiving a first subsequence of data words corresponding to a currently owned data line and for claiming ownership in one or more of the very next data lines corresponding to the next subsequences of data words to be transferred from the I/O device. The I/O bridge also has a buffer memory for storing a subsequence of the sequence of data words received from the I/O device. The control logic maintains in a pre-own tag array a list of the data lines in which ownership has been successfully claimed and a list in a buffer tag array of storage locations in the buffer memory allocated to receiving data words of particular subsequences of the sequence of data words from the I/O device.
摘要翻译：公开了一种用于通过I / O桥将数据字序列从I / O设备有效传送到主存储器中的顺序地址的方法和系统。要传送的数据字的序列包括数据字的一个或多个子序列。数据字的每个子序列仅包括去往仅存储一条数据线的数据字的主存储器地址的数据字。 I / O桥具有用于接收对应于当前所拥有的数据线的数据字的第一子序列的控制逻辑，并且用于在与要传送的数据字的下一个子序列相对应的下一个数据线中的一个或多个中 I / O设备。 I / O桥还具有用于存储从I / O设备接收的数据字序列的子序列的缓冲存储器。控制逻辑在自己前的标签阵列中保持所有权已被成功声明的数据线的列表以及被分配用于接收该序列的特定子序列的数据字的缓冲存储器中的存储位置的缓冲器标签阵列中的列表来自I / O设备的数据字。

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