专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06649995B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06649995B2
公开(公告)日：2003-11-18
申请号：US10126542
申请日：2002-04-22
申请人： Shigeo Tooi , Katsumi Satoh
发明人： Shigeo Tooi , Katsumi Satoh
IPC分类号： H01L2947
CPC分类号： H01L24/85 , H01L23/488 , H01L24/03 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/72 , H01L29/872 , H01L2224/04042 , H01L2224/05647 , H01L2224/32225 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/4845 , H01L2224/48463 , H01L2224/48491 , H01L2224/48647 , H01L2224/48747 , H01L2224/73265 , H01L2224/85205 , H01L2924/00014 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01028 , H01L2924/01029 , H01L2924/01031 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/014 , H01L2924/10272 , H01L2924/12032 , H01L2924/12036 , H01L2924/19043 , H01L2924/351 , H01L2224/78 , H01L2924/00 , H01L2924/00015
摘要： A Schottky diode that achieves a predetermined reverse-direction breakdown voltage even if a state of a surface in a vicinity of a Schottky junction interface changes due to a welding of a bonding wire. The semiconductor device having the Schottky junction includes a semiconductor substrate of a first conductivity type. A well region of a second conductivity type is formed in a top surface of the semiconductor substrate. A Schottky electrode is formed on the top surface of the semiconductor substrate. A connecting conductive member is electrically connected to the Schottky electrode. The connecting conductive member is selectively connected to the Schottky electrode above the well region such that a connection surface between the connecting conductive member and the Schottky electrode is not extended above a Schottky junction between the Schottky electrode and the semiconductor substrate of the first conductivity type.
摘要翻译：即使肖特基结界面附近的表面的状态由于接合线的焊接而变化，也能够实现预定的反向击穿电压的肖特基二极管。具有肖特基结的半导体器件包括第一导电类型的半导体衬底。第二导电类型的阱区形成在半导体衬底的顶表面中。肖特基电极形成在半导体衬底的顶表面上。连接导电部件与肖特基电极电连接。连接导电构件选择性地连接到阱区上方的肖特基电极，使得连接导电构件和肖特基电极之间的连接表面不延伸到肖特基电极和第一导电类型的半导体衬底之间的肖特基结之上。

2. 发明申请

US20110133312A1 POWER DEVICE 有权
标题翻译：电源设备
公开(公告)号：US20110133312A1
公开(公告)日：2011-06-09
申请号：US13058544
申请日：2008-10-14
申请人： Shigeo Tooi , Tetsujiro Tsunoda
发明人： Shigeo Tooi , Tetsujiro Tsunoda
IPC分类号： H01L29/739
CPC分类号： H01L29/7395 , H01L29/0661 , H01L29/1095
摘要： The present invention is a power device includes, a first conductive type semiconductor substrate, a second conductive type base region formed on a surface of the semiconductor substrate, a second conductive type collector region formed on a rear surface of the semiconductor substrate, a first conductive type emitter region formed on a surface of the base region, a trench gate formed via a gate insulating film in a first trench groove formed in the base region so as to penetrate the emitter region, a dent formed in the base region in proximity to the emitter region, a second conductive type contact layer formed on an inner wall of the dent, having a higher dopant density than that of the base region, a dummy trench formed via a dummy trench insulating film in a second trench groove formed at a bottom of the dent, and an emitter electrode electrically connected to the emitter region, the contact layer and the dummy trench, wherein the trench gate and the dummy trench reach the semiconductor substrate.
摘要翻译：本发明是一种功率器件，包括第一导电型半导体衬底，形成在半导体衬底的表面上的第二导电型基极区域，形成在半导体衬底的后表面上的第二导电类型集电极区域，第一导电类型形成在基极区域的表面上的栅极型发射极区域，形成在基极区域中的第一沟槽中的栅极绝缘膜的沟槽栅极，以穿透发射极区域，形成在基极区域附近的凹陷发射极区域，形成在凹陷内壁上的第二导电类型接触层，具有比基极区域更高的掺杂剂密度;在第二沟槽沟槽中形成的虚设沟槽，所述第二沟槽沟槽形成在底部凹陷和电连接到发射极区域的发射极电极，接触层和虚设沟槽，其中沟槽栅极和虚拟沟槽到达半导体 ctor底物。

3. 发明授权

US07057298B2 Semiconductor device with semiconductor chip formed by using wide gap semiconductor as base material 有权
标题翻译：具有通过使用宽间隙半导体作为基材形成的半导体芯片的半导体器件
公开(公告)号：US07057298B2
公开(公告)日：2006-06-06
申请号：US11007246
申请日：2004-12-09
申请人： Masayoshi Hirao , Katsumi Satou , Shigeo Tooi , Kazushige Matsuo
发明人： Masayoshi Hirao , Katsumi Satou , Shigeo Tooi , Kazushige Matsuo
IPC分类号： H01L23/02
CPC分类号： H01L25/18 , H01L23/051 , H01L23/36 , H01L25/072 , H01L2924/0002 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： A switching chip using silicon as the base material is located on the upper surface of a cooling mechanism formed of a heat sink, an insulating substrate and a conductive plate, with a first conductive layer sandwiched in between. Further, a diode chip having a smaller area than a cathode electrode and using a wide gap semiconductor as the base material is located on the cathode electrode which has a smaller area than an anode electrode, with a second conductive layer sandwiched in between. A closed container encloses every structural component except an exposed portion of a bottom surface in the interior space.
摘要翻译：使用硅作为基材的开关芯片位于由散热器，绝缘基板和导电板形成的冷却机构的上表面上，第一导电层夹在其间。此外，具有比阴极电极小的面积和使用宽间隙半导体作为基底材料的二极管芯片位于具有比阳极电极小的面积的阴极上，其间夹有第二导电层。封闭的容器包围除了内部空间中的底部表面的暴露部分之外的每个结构部件。

4. 发明申请

US20050098876A1 Semiconductor device with semiconductor chip formed by using wide gap semiconductor as base material 有权
标题翻译：具有通过使用宽间隙半导体作为基材形成的半导体芯片的半导体器件
公开(公告)号：US20050098876A1
公开(公告)日：2005-05-12
申请号：US11007246
申请日：2004-12-09
申请人： Masayoshi Hirao , Katsumi Satou , Shigeo Tooi , Kazushige Matsuo
发明人： Masayoshi Hirao , Katsumi Satou , Shigeo Tooi , Kazushige Matsuo
IPC分类号： H01L23/34 , H01L21/52 , H01L23/051 , H01L23/36 , H01L25/07 , H01L25/18 , H01L29/22
CPC分类号： H01L25/18 , H01L23/051 , H01L23/36 , H01L25/072 , H01L2924/0002 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： A switching chip using silicon as the base material is located on the upper surface of a cooling mechanism formed of a heat sink, an insulating substrate and a conductive plate, with a first conductive layer sandwiched in between. Further, a diode chip having a smaller area than a cathode electrode and using a wide gap semiconductor as the base material is located on the cathode electrode which has a smaller area than an anode electrode, with a second conductive layer sandwiched in between. A closed container encloses every structural component except an exposed portion of a bottom surface in the interior space.
摘要翻译：使用硅作为基材的开关芯片位于由散热器，绝缘基板和导电板形成的冷却机构的上表面上，第一导电层夹在其间。此外，具有比阴极电极小的面积和使用宽间隙半导体作为基底材料的二极管芯片位于具有比阳极电极小的面积的阴极上，其间夹有第二导电层。封闭的容器包围除了内部空间中的底部表面的暴露部分之外的每个结构部件。

5. 发明授权

US06861730B2 Semiconductor device with semiconductor chip formed by using wide gap semiconductor as base material 有权
标题翻译：具有通过使用宽间隙半导体作为基材形成的半导体芯片的半导体器件
公开(公告)号：US06861730B2
公开(公告)日：2005-03-01
申请号：US10786095
申请日：2004-02-26
申请人： Masayoshi Hirao , Katsumi Satou , Shigeo Tooi , Kazushige Matsuo
发明人： Masayoshi Hirao , Katsumi Satou , Shigeo Tooi , Kazushige Matsuo
IPC分类号： H01L23/34 , H01L21/52 , H01L23/051 , H01L23/36 , H01L25/07 , H01L25/18 , H01L29/06
CPC分类号： H01L25/18 , H01L23/051 , H01L23/36 , H01L25/072 , H01L2924/0002 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： A switching chip (101) using silicon as the base material is located on the upper surface of a cooling mechanism formed of a heat sink (115), an insulating substrate (114) and a conductive plate (108), with a first conductive layer (109A) sandwiched in between. Further, a diode chip (102) having a smaller area than a cathode electrode (103) and using a wide gap semiconductor as the base material is located on the cathode electrode (103) which has a smaller area than an anode electrode (105), with a second conductive layer (109B) sandwiched in between. A closed container (117) encloses every structural component except an exposed portion of a bottom surface (115BS) in the interior space.
摘要翻译：使用硅作为基材的开关芯片（101）位于由散热器（115），绝缘基板（114）和导电板（108）形成的冷却机构的上表面上，第一导电层（109A）。此外，具有比阴极电极（103）更小的面积并且使用宽间隙半导体作为基材的二极管芯片（102）位于具有比阳极电极（105）更小的面积的阴极电极（103）上，具有夹在其间的第二导电层（109B）。封闭的容器（117）围绕除了内部空间中的底部表面（115BS）的暴露部分之外的每个结构部件。

6. 发明授权

US08129818B2 Power device 有权
标题翻译：电源设备
公开(公告)号：US08129818B2
公开(公告)日：2012-03-06
申请号：US13058544
申请日：2008-10-14
申请人： Shigeo Tooi , Tetsujiro Tsunoda
发明人： Shigeo Tooi , Tetsujiro Tsunoda
IPC分类号： H01L29/739
CPC分类号： H01L29/7395 , H01L29/0661 , H01L29/1095
摘要： The present invention is a power device includes, a first conductive type semiconductor substrate, a second conductive type base region formed on a surface of the semiconductor substrate, a second conductive type collector region formed on a rear surface of the semiconductor substrate, a first conductive type emitter region formed on a surface of the base region, a trench gate formed via a gate insulating film in a first trench groove formed in the base region so as to penetrate the emitter region, a dent formed in the base region in proximity to the emitter region, a second conductive type contact layer formed on an inner wall of the dent, having a higher dopant density than that of the base region, a dummy trench formed via a dummy trench insulating film in a second trench groove formed at a bottom of the dent, and an emitter electrode electrically connected to the emitter region, the contact layer and the dummy trench, wherein the trench gate and the dummy trench reach the semiconductor substrate.
摘要翻译：本发明是一种功率器件，包括第一导电型半导体衬底，形成在半导体衬底的表面上的第二导电型基极区域，形成在半导体衬底的后表面上的第二导电类型集电极区域，第一导电类型形成在基极区域的表面上的栅极型发射极区域，形成在基极区域中的第一沟槽中的栅极绝缘膜的沟槽栅极，以穿透发射极区域，形成在基极区域附近的凹陷发射极区域，形成在凹陷内壁上的第二导电类型接触层，具有比基极区域更高的掺杂剂密度;在第二沟槽沟槽中形成的虚设沟槽，所述第二沟槽沟槽形成在底部凹陷和电连接到发射极区域的发射极电极，接触层和虚设沟槽，其中沟槽栅极和虚拟沟槽到达半导体 ctor底物。

7. 发明授权

US07772669B2 Semiconductor device having an improved structure for high withstand voltage 失效
标题翻译：具有改进的高耐压结构的半导体器件
公开(公告)号：US07772669B2
公开(公告)日：2010-08-10
申请号：US11540625
申请日：2006-10-02
申请人： Shigeo Tooi , Tetsujiro Tsunoda
发明人： Shigeo Tooi , Tetsujiro Tsunoda
IPC分类号： H01L29/93
CPC分类号： H01L29/7395 , H01L29/0619 , H01L29/0638 , H01L29/0834 , H01L29/402
摘要： Second diffusion layers to be guard rings of a second conductivity type are formed on the major surface of a semiconductor substrate of a first conductivity type in a guard ring region. An insulating film is formed on these second diffusion layers. The semiconductor device has a structure wherein a conductive film is formed on the insulating film between adjacent electrodes among a first surface electrode, second surface electrodes, and a third surface electrode.
摘要翻译：在保护环区域中的第一导电类型的半导体衬底的主表面上形成第二导电类型的保护环的第二扩散层。在这些第二扩散层上形成绝缘膜。半导体器件具有其中在第一表面电极，第二表面电极和第三表面电极中的相邻电极之间的绝缘膜上形成导电膜的结构。

8. 发明申请

US20070278672A1 Semiconductor device having an improved structure for high withstand voltage 失效
标题翻译：具有改进的高耐压结构的半导体器件
公开(公告)号：US20070278672A1
公开(公告)日：2007-12-06
申请号：US11540625
申请日：2006-10-02
申请人： Shigeo Tooi , Tetsujiro Tsunoda
发明人： Shigeo Tooi , Tetsujiro Tsunoda
IPC分类号： H01L21/44
CPC分类号： H01L29/7395 , H01L29/0619 , H01L29/0638 , H01L29/0834 , H01L29/402
摘要： Second diffusion layers to be guard rings of a second conductivity type are formed on the major surface of a semiconductor substrate of a first conductivity type in a guard ring region. An insulating film is formed on these second diffusion layers. The semiconductor device has a structure wherein a conductive film is formed on the insulating film between adjacent electrodes among a first surface electrode, second surface electrodes, and a third surface electrode.
摘要翻译：在保护环区域中的第一导电类型的半导体衬底的主表面上形成第二导电类型的保护环的第二扩散层。在这些第二扩散层上形成绝缘膜。半导体器件具有其中在第一表面电极，第二表面电极和第三表面电极中的相邻电极之间的绝缘膜上形成导电膜的结构。

9. 发明授权

US06831351B2 Semiconductor device with semiconductor chip formed by using wide gap semiconductor as base material 有权
标题翻译：具有半导体芯片的半导体器件采用宽间隙半导体作为基底材料形成
公开(公告)号：US06831351B2
公开(公告)日：2004-12-14
申请号：US10208980
申请日：2002-08-01
申请人： Masayoshi Hirao , Katsumi Satou , Shigeo Tooi , Kazushige Matsuo
发明人： Masayoshi Hirao , Katsumi Satou , Shigeo Tooi , Kazushige Matsuo
IPC分类号： H01L2906
CPC分类号： H01L25/18 , H01L23/051 , H01L23/36 , H01L25/072 , H01L2924/0002 , H01L2924/13055 , H01L2924/13091 , H01L2924/00
摘要： A switching chip (101) using silicon as the base material is located on the upper surface of a cooling mechanism formed of a heat sink (115), an insulating substrate (114) and a conductive plate (108), with a first conductive layer (109A) sandwiched in between. Further, a diode chip (102) having a smaller area than a cathode electrode (103) and using a wide gap semiconductor as the base material is located on the cathode electrode (103) which has a smaller area than an anode electrode (105), with a second conductive layer (109B) sandwiched in between. A closed container (117) encloses every structural component except an exposed portion of a bottom surface (115BS) in the interior space.
摘要翻译：使用硅作为基材的开关芯片（101）位于由散热器（115），绝缘基板（114）和导电板（108）形成的冷却机构的上表面上，第一导电层（109A）。此外，具有比阴极电极（103）更小的面积并且使用宽间隙半导体作为基材的二极管芯片（102）位于具有比阳极电极（105）更小的面积的阴极电极（103）上，具有夹在其间的第二导电层（109B）。封闭的容器（117）围绕除了内部空间中的底部表面（115BS）的暴露部分之外的每个结构部件。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式