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1. 发明申请

US20070136616A1 Memory card 审中-公开
标题翻译：存储卡
公开(公告)号：US20070136616A1
公开(公告)日：2007-06-14
申请号：US11703745
申请日：2007-02-08
申请人： Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori , Atsushi Shikata , Tetsuya Iida
发明人： Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori , Atsushi Shikata , Tetsuya Iida
IPC分类号： G06F1/00
CPC分类号： G06K19/0701 , G06K19/07
摘要： A memory card is provided in which power consumption is reduced by the pull-up resistor of an input terminal and a misoperation induced by the pull-down resistor of a host apparatus is prevented. The memory card has a select terminal connected to the pull-up resistor. When the mode of the memory card is determined based on an input from the select terminal, a relatively low resistance value is selected for the pull-up resistor of the select terminal before a determination timing and the pull-up resistor is restored to an initial resistance value after the mode determination. A relatively high resistance value reduces a leakage current consumed by the pull-up resistor of the select terminal. When a pull-down resistor is connected to the terminal of a memory card host to which the memory card is attached, if the resistance value of the pull-up resistor is excessively high, it is influenced by the drawing in of a current by the pull-down resistor. If the resistance value of the pull-up resistor of the select terminal is lowered at the time of mode determination, an adverse effect of the lowering of a potential by the pull-down resistor can be circumvented.
摘要翻译：提供了一种存储卡，其中通过输入端的上拉电阻降低功耗，并且防止由主机设备的下拉电阻引起的误操作。存储卡具有连接到上拉电阻的选择端子。当基于来自选择端子的输入确定存储卡的模式时，在确定定时之前为选择端的上拉电阻选择相对较低的电阻值，并且将上拉电阻恢复到初始值模式确定后的电阻值。相对较高的电阻值减小了选择端子的上拉电阻消耗的漏电流。当下拉电阻连接到与存储卡相连的存储卡主机的端子时，如果上拉电阻的电阻值过高，则会受到电流的影响下拉电阻。如果选择端子的上拉电阻的电阻值在模式确定时降低，则可以避免下拉电阻降低电位的不利影响。

2. 发明授权

US07188265B2 Method of recognizing a card using a select signal during a determination mode and switching from low to high resistance after the determination 有权
标题翻译：在确定模式期间使用选择信号识别卡并在确定之后从低电平切换到高电阻的方法
公开(公告)号：US07188265B2
公开(公告)日：2007-03-06
申请号：US10716456
申请日：2003-11-20
申请人： Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori , Atsushi Shikata , Tetsuya Iida
发明人： Shigeo Kurakata , Kunihiro Katayama , Motoki Kanamori , Atsushi Shikata , Tetsuya Iida
IPC分类号： G06F1/26
CPC分类号： G06K19/0701 , G06K19/07
摘要： A memory card is provided in which power consumption is reduced by the pull-up resistor of an input terminal and a misoperation induced by the pull-down resistor of a host apparatus is prevented. The memory card has a select terminal connected to the pull-up resistor. When the mode of the memory card is determined based on an input from the select terminal, a relatively low resistance value is selected for the pull-up resistor of the select terminal before a determination timing and the pull-up resistor is restored to an initial resistance value after the mode determination. A relatively high resistance value reduces a leakage current consumed by the pull-up resistor of the select terminal. When a pull-down resistor is connected to the terminal of a memory card host to which the memory card is attached, if the resistance value of the pull-up resistor is excessively high, it is influenced by the drawing in of a current by the pull-down resistor. If the resistance value of the pull-up resistor of the select terminal is lowered at the time of mode determination, an adverse effect of the lowering of a potential by the pull-down resistor can be circumvented.
摘要翻译：提供了一种存储卡，其中通过输入端的上拉电阻降低功耗，并且防止由主机设备的下拉电阻引起的误操作。存储卡具有连接到上拉电阻的选择端子。当基于来自选择端子的输入确定存储卡的模式时，在确定定时之前为选择端的上拉电阻选择相对较低的电阻值，并且将上拉电阻恢复到初始值模式确定后的电阻值。相对较高的电阻值减小了选择端子的上拉电阻消耗的漏电流。当下拉电阻连接到与存储卡相连的存储卡主机的端子时，如果上拉电阻的电阻值过高，则会受到电流的影响下拉电阻。如果选择端子的上拉电阻的电阻值在模式确定时降低，则可以避免下拉电阻降低电位的不利影响。

3. 发明授权

US06972979B2 Nonvolatile memory 有权
公开(公告)号：US06972979B2
公开(公告)日：2005-12-06
申请号：US10716504
申请日：2003-11-20
申请人： Tetsuya Iida , Motoki Kanamori , Atsushi Shikata , Takayuki Tamura , Kunihiro Katayama
发明人： Tetsuya Iida , Motoki Kanamori , Atsushi Shikata , Takayuki Tamura , Kunihiro Katayama
IPC分类号： G06K19/077 , G06K19/06 , G06K19/07 , G11C5/02 , G11C7/00 , G11C16/04 , G11C16/06
CPC分类号： G06K19/07732 , G06K19/07
摘要： There is provided a technology to realize high speed data transfer while compatibility of a card type storage device comprising a nonvolatile memory is ensured. Namely, in the card type storage device comprising the nonvolatile memory, a plurality of data terminals are provided and an interface unit is provided with a circuit for determining levels of data terminals. Some or all of the plurality of data terminals are connected with pull-up resistors for pulling up to a power source voltage. When the determination circuit determines that the data terminals connected with the pull-up resistors are in an open condition, the determination circuit switches a bus width (number of bits) of data.

4. 发明申请

US20050211786A1 Nonvolatile memory 审中-公开
标题翻译：非易失性存储器
公开(公告)号：US20050211786A1
公开(公告)日：2005-09-29
申请号：US11131292
申请日：2005-05-18
申请人： Tetsuya Iida , Motoki Kanamori , Atsushi Shikata , Takayuki Tamura , Kunihiro Katayama
发明人： Tetsuya Iida , Motoki Kanamori , Atsushi Shikata , Takayuki Tamura , Kunihiro Katayama
IPC分类号： G06K19/077 , G06K19/06 , G06K19/07 , G11C5/02 , G11C7/00 , G11C16/04 , G11C16/06
CPC分类号： G06K19/07732 , G06K19/07
摘要： There is provided a technology to realize high speed data transfer while compatibility of a card type storage device comprising a nonvolatile memory is ensured. Namely, in the card type storage device comprising the nonvolatile memory, a plurality of data terminals are provided and an interface unit is provided with a circuit for determining levels of data terminals. Some or all of the plurality of data terminals are connected with pull-up resistors for pulling up to a power source voltage. When the determination circuit determines that the data terminals connected with the pull-up resistors are in an open condition, the determination circuit switches a bus width (number of bits) of data.
摘要翻译：提供了一种实现高速数据传输的技术，同时确保包括非易失性存储器的卡式存储装置的兼容性。也就是说，在包括非易失性存储器的卡型存储装置中，提供多个数据终端，并且接口单元设置有用于确定数据终端电平的电路。多个数据端子中的一些或全部与上拉电阻相连以提升电源电压。当确定电路确定与上拉电阻器连接的数据端子处于打开状态时，确定电路切换数据的总线宽度（位数）。

5. 发明申请

US20050185463A1 Nonvolatile memory and data processing system 审中-公开
标题翻译：非易失性存储器和数据处理系统
公开(公告)号：US20050185463A1
公开(公告)日：2005-08-25
申请号：US11058672
申请日：2005-02-16
申请人： Motoki Kanamori , Shinichi Fukasawa , Shigeo Kurakata , Tetsuya Iida , Shinsuke Asari
发明人： Motoki Kanamori , Shinichi Fukasawa , Shigeo Kurakata , Tetsuya Iida , Shinsuke Asari
IPC分类号： B42D15/10 , G06F12/14 , G06K17/00 , G06K19/00 , G11C11/34 , G11C16/20 , G11C16/22
CPC分类号： G11C16/20 , G11C16/22 , G11C2216/30
摘要： The present invention provides a nonvolatile memory which includes a card controller, a reprogrammable nonvolatile memory and an IC card chip. The card controller is capable of outputting at least one of reset response information (ATR) outputted from the IC card chip in response to a reset instruction to the IC card chip and information indicative of an erase unit of a flash memory to the outside in response to a predetermined command supplied from outside. A card host is capable of causing the card controller to change an operating speed or operating frequency or the like of the IC card chip by reference to the ATR information. Upon reprogramming of memory information with respect to the reprogrammable nonvolatile memory, the card host is capable of sending write data equivalent to an amount commensurate with an erase unit to the nonvolatile memory by reference to the information indicative of the erase unit and giving write instructions.
摘要翻译：本发明提供一种非易失性存储器，其包括卡控制器，可再编程非易失性存储器和IC卡芯片。卡控制器能够响应于对IC卡芯片的复位指令和指示闪存的擦除单元的信息从外部输出从IC卡芯片输出的复位响应信息（ATR）中的至少一个作为响应到从外部提供的预定命令。卡主机能够通过参考ATR信息使卡控制器改变IC卡芯片的操作速度或操作频率等。在对可再编程的非易失性存储器进行存储器信息的重新编程时，卡主机能够通过参考指示擦除单元的信息并给出写指令，将与擦除单元相当的量的写入数据发送到非易失性存储器。

6. 发明申请

US20070045426A1 Memory card 审中-公开
标题翻译：存储卡
公开(公告)号：US20070045426A1
公开(公告)日：2007-03-01
申请号：US11512126
申请日：2006-08-30
申请人： Shigemasa Shiota , Satoshi Yoshida , Shigeo Kurakata , Shinsuke Asari , Tetsuya Iida
发明人： Shigemasa Shiota , Satoshi Yoshida , Shigeo Kurakata , Shinsuke Asari , Tetsuya Iida
IPC分类号： G06K19/06
CPC分类号： G06F13/4239 , Y02D10/14 , Y02D10/151
摘要： The present invention is directed to suppress propagation of noise from an interface controller to an IC card microcomputer. A memory card of the invention includes an external terminal, an IC card terminal, an interface controller connected to the external terminal, a memory device connected to the interface controller, and an IC card microcomputer connected to the interface controller. The interface controller controls operation of the memory device and the IC card microcomputer in response to an input from the external terminal. The IC card terminal is directly connected to a connection line between the interface controller and the IC card microcomputer. When operation of the IC card microcomputer responding to an input from the IC card terminal is permitted in parallel with operation responding to an input from the external terminal, the interface controller sets an output buffer in the interface controller connected to the connection line into a high impedance state.
摘要翻译：本发明旨在抑制噪声从接口控制器传播到IC卡微计算机。本发明的存储卡包括外部端子，IC卡端子，连接到外部端子的接口控制器，连接到接口控制器的存储器件以及连接到接口控制器的IC卡微计算机。接口控制器响应于来自外部端子的输入来控制存储器件和IC卡微计算机的操作。 IC卡终端直接连接到接口控制器和IC卡微机之间的连接线。当响应于来自外部终端的输入的操作并行地执行响应于来自IC卡终端的输入的IC卡微计算机的操作时，接口控制器将连接到连接线的接口控制器中的输出缓冲器设置为高阻抗状态。

7. 发明申请

US20080245878A1 IC CARD 审中-公开
标题翻译： IC卡
公开(公告)号：US20080245878A1
公开(公告)日：2008-10-09
申请号：US12050926
申请日：2008-03-18
申请人： Shigemasa SHIOTA , Shigeo Kurakata , Shinsuke Asari , Tetsuya Iida , Shinichi Fukasawa
发明人： Shigemasa SHIOTA , Shigeo Kurakata , Shinsuke Asari , Tetsuya Iida , Shinichi Fukasawa
IPC分类号： G06K19/067
CPC分类号： G06K19/07 , G06K19/07732
摘要： Disclosed is a semiconductor device including built-in interface circuits whose operations are selected in response to initialization operation from a host apparatus coupled thereto. In the semiconductor device, a first synchronous interface circuit and a second asynchronous interface circuit using differential signals, share the external terminals of the differential signals (the external differential signal terminals). For example, the semiconductor device adopts an MMC interface circuit as the first interface circuit and a USB interface circuit as the second interface circuit, while keeping the IC card interface function. The semiconductor device selects operations of the adopted interface circuits exclusively. One selection method is to enable an interface operation of the first interface circuit, upon detection of a plurality of edge changes in a clock input from an external clock terminal, which is for initializing the first interface circuit when power supply to the semiconductor device is started.
摘要翻译：公开了一种包括内置接口电路的半导体器件，其操作是响应于与其耦合的主机设备的初始化操作来选择的。在半导体器件中，使用差分信号的第一同步接口电路和第二异步接口电路共享差分信号的外部端子（外部差分信号端子）。例如，半导体器件采用MMC接口电路作为第一接口电路和USB接口电路作为第二接口电路，同时保持IC卡接口功能。半导体器件专门选择所采用的接口电路的操作。一种选择方法是在检测到从外部时钟端子输入的时钟中的多个边缘变化时启用第一接口电路的接口操作，其用于在开始向半导体器件供电时初始化第一接口电路。

8. 发明申请

US20140199894A1 CONNECTING APPARATUS FOR POWER CABLE 有权
标题翻译：电源线连接装置
公开(公告)号：US20140199894A1
公开(公告)日：2014-07-17
申请号：US14152639
申请日：2014-01-10
申请人： Haruki Kusamaki , Tetsuya Iida , Hiroyuki Matsuoka , Takuya Tate
发明人： Haruki Kusamaki , Tetsuya Iida , Hiroyuki Matsuoka , Takuya Tate
IPC分类号： H01R9/24
CPC分类号： H01R9/24 , H01R4/34
摘要： The cables are configured to supply electric power from an inverter to a motor. The cables include a connector and plural terminals fixed to the connector. A housing of the connector includes a first rib, provided between the adjacent terminals, connecting mutually facing surfaces of the housing. The terminal block is attached to an enclosure of the inverter or motor. The terminal block includes plural retaining walls, each of which encloses and retains a nut. The terminal block includes a second rib connecting adjacent retaining walls. One of the first and second ribs includes a recess. The connector is connected to the terminal block when each of the terminals is fastened to the terminal block with a bolt and the nut. The other of the first and second ribs is disposed in the recess and the ribs intersect when the connector is connected to the terminal block.
摘要翻译：电缆被配置为从逆变器向电动机提供电力。电缆包括连接器和固定到连接器的多个端子。连接器的壳体包括设置在相邻端子之间的第一肋，连接壳体的相互面对的表面。端子块连接到变频器或电机的外壳。端子块包括多个保持壁，每个保持壁包围并保持螺母。端子块包括连接相邻挡土墙的第二肋。第一和第二肋中的一个包括凹部。当每个端子用螺栓和螺母紧固到端子块时，连接器连接到端子块。第一和第二肋中的另一个设置在凹部中，并且当连接器连接到端子块时，肋相交。

9. 发明申请

US20090159974A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090159974A1
公开(公告)日：2009-06-25
申请号：US12251790
申请日：2008-10-15
申请人： Hideyuki Ono , Tetsuya Iida
发明人： Hideyuki Ono , Tetsuya Iida
IPC分类号： H01L27/06
CPC分类号： H01L27/0629 , H01L27/0255 , H01L29/0692 , H01L29/4175 , H01L29/66121 , H01L29/66659 , H01L29/7835 , H01L29/861 , H01L29/8611 , H03F1/523 , H03F3/195 , H03F2200/444
摘要： A high-frequency power amplifier of the type to be mounted in an RF module for mobile phones having high-frequency power field effect transistors and gate protective diodes which are coupled between the gates and the sources of the high-frequency power field effect transistors. The gate protective diodes have an n type region formed over the main surface of a p type epitaxial layer, a first p type region formed at the center of the main surface of the n type region, a second p type region formed over the main surface of the epitaxial layer around the n type region from the periphery of the main surface of the n type region, and p+ type buried layers for coupling the second p type region to a substrate body. The distance between the end portions of the p+ type buried layers and the n+ type region is 7 μm or more.
摘要翻译：一种高频功率放大器，其类型安装在具有高频功率场效应晶体管和栅极保护二极管的移动电话的RF模块中，高频功率场效应晶体管和栅极保护二极管耦合在高频功率场效应晶体管的栅极和源极之间。栅极保护二极管具有形成在p型外延层的主表面上的n型区域，形成在n型区域的主表面中心的第一p型区域，形成在n型区域的主表面上的第二p型区域从n型区域的主表面周围的n型区域周围的外延层和用于将第二p型区域耦合到衬底本体的p +型掩埋层。 p +型掩埋层和n +型区域的端部之间的距离为7μm以上。

10. 发明申请

US20080312228A1 PYRIMIDINE COMPOUND AND MEDICAL USE THEREOF 审中-公开
标题翻译：吡嗪类化合物及其医疗用途
公开(公告)号：US20080312228A1
公开(公告)日：2008-12-18
申请号：US12053133
申请日：2008-03-21
申请人： Hisashi Kawasaki , Hiroyuki Abe , Kazuhide Hayakawa , Tetsuya Iida , Shinichi Kikuchi , Takayuki Yamaguchi , Toyomichi Nanayama , Hironori Kurachi , Masahiro Tamaru , Yoshikazu Hori , Mitsuru Takahashi , Takayuki Yoshida , Toshiyuki Sakai
发明人： Hisashi Kawasaki , Hiroyuki Abe , Kazuhide Hayakawa , Tetsuya Iida , Shinichi Kikuchi , Takayuki Yamaguchi , Toyomichi Nanayama , Hironori Kurachi , Masahiro Tamaru , Yoshikazu Hori , Mitsuru Takahashi , Takayuki Yoshida , Toshiyuki Sakai
IPC分类号： C07D487/04 , A61K31/519 , A61K31/5377 , A61K31/496 , A61P35/00
CPC分类号： C07D471/04 , A61K31/519 , C07C275/30 , C07C275/50 , C07C2601/16 , C07D239/545 , C07D239/553 , C07D239/62 , C07D471/16 , C07D487/04 , C07F9/53
摘要： The present invention relates to a pyrimidine compound or a pharmaceutically acceptable salt thereof represented by the following formula [I] wherein each symbol is as defined in the specification and a method of therapeutically or prophylactically treating an undesirable cell proliferation, comprising administering such a compound. The compound of the present invention has superior activity in suppressing undesirable cell proliferation, particularly, an antitumor activity, and is useful as an antitumor agent for the prophylaxis or treatment of cancer, rheumatism, and the like. In addition, the compound of the present invention can be a more effective antitumor agent when used in combination with other antitumor agents such as an alkylating agent or metabolism antagonist.
摘要翻译：本发明涉及由下式[I]表示的嘧啶化合物或其药学上可接受的盐，其中每个符号如说明书中所定义，以及治疗或预防性治疗不期望的细胞增殖的方法，包括施用这种化合物。本发明的化合物在抑制不期望的细胞增殖，特别是抗肿瘤活性方面具有优异的活性，可用作预防或治疗癌症，风湿病等的抗肿瘤剂。此外，当与其它抗肿瘤剂如烷化剂或代谢拮抗剂组合使用时，本发明的化合物可以是更有效的抗肿瘤剂。

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