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1. 发明授权

US06953979B1 Semiconductor device, method of manufacturing same and method of designing same 失效
标题翻译：半导体装置及其制造方法及其设计方法
公开(公告)号：US06953979B1
公开(公告)日：2005-10-11
申请号：US09466934
申请日：1999-12-20
申请人： Yasuo Yamaguchi , Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Takuji Matsumoto , Shoichi Miyamoto
发明人： Yasuo Yamaguchi , Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Takuji Matsumoto , Shoichi Miyamoto
IPC分类号： H01L21/762 , H01L21/331 , H01L21/8238 , H01L21/84 , H01L27/01 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/786 , H01L31/00
CPC分类号： H01L21/84 , H01L27/1203
摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.
摘要翻译：在其之间形成的具有阱区的部分氧化物膜（31）将SOI层（3）中的晶体管形成区域彼此隔离。在部分氧化膜（31）的下部形成p型阱区（11），其将NMOS晶体管彼此隔离，并且在部分氧化膜（31）的一部分下方形成n型阱区（12）），其将PMOS晶体管彼此隔离。 p型阱区（11）和n型阱区（12）在部分氧化膜（31）的下部并排形成，其提供NMOS和PMOS晶体管之间的隔离。身体区域与与其相邻的井区域（11）接触。形成在层间绝缘膜（4）上的互连层通过设置在层间绝缘膜（4）中的主体接触部电连接到体区。具有SOI结构的半导体器件减少浮置衬底效应。

2. 发明授权

US07608879B2 Semiconductor device including a capacitance 有权
标题翻译：包括电容的半导体装置
公开(公告)号：US07608879B2
公开(公告)日：2009-10-27
申请号：US11840612
申请日：2007-08-17
申请人： Shigenobu Maeda , Takashi Ipposhi , Yuuichi Hirano
发明人： Shigenobu Maeda , Takashi Ipposhi , Yuuichi Hirano
IPC分类号： H01L29/94
CPC分类号： H01L21/84 , H01L27/0629 , H01L27/0808 , H01L27/0811 , H01L27/1203 , H01L29/66181 , H01L29/66545 , H01L29/94
摘要： It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer portion of the SOI layer (171) with a part of the SOI layer (171) remaining as a P− well region (169). Consequently, an isolation (partial isolation) structure is obtained. An N+ diffusion region (168) is formed in the SOI layer (171) between the isolating oxide films (167a) and (167b) and a P+ diffusion region (170) is formed in the SOI layer (171) between the isolating oxide films (167b) and (167c). Consequently, there is obtained a junction type variable capacitance (C23) having a PN junction surface of the P− well region (169) provided under the isolating oxide film (167b) and the N+ diffusion region (168).
摘要翻译：本发明的目的是获得包括具有大Q值的电容的半导体器件。在包括支撑衬底（165），掩埋氧化膜（166）和SOI层（171）的SOI衬底中，在SOI层的上层部分中选择性地形成隔离氧化膜167（167a至167c） 171）与SOI层（171）的一部分保持为P-阱区域（169）。因此，获得隔离（部分隔离）结构。在隔离氧化膜（167a）和（167b）之间的SOI层（171）中形成N +扩散区（168），在SOI层（171）中形成P +扩散区（170）（167b）和（167c）。因此，获得了在隔离氧化膜（167b）和N +扩散区（168）之下具有P-阱区（169）的PN结表面的结型可变电容（C23）。

3. 发明申请

US20050156242A1 Semiconductor device, method of manufacturing same and method of designing same 有权
公开(公告)号：US20050156242A1
公开(公告)日：2005-07-21
申请号：US11034938
申请日：2005-01-14
申请人： Yasuo Yamaguchi , Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Takuji Matsumoto , Shoichi Miyamoto
发明人： Yasuo Yamaguchi , Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Takuji Matsumoto , Shoichi Miyamoto
IPC分类号： H01L21/762 , H01L21/331 , H01L21/8238 , H01L21/84 , H01L27/01 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/786 , H01L31/00
CPC分类号： H01L21/84 , H01L27/1203
摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

4. 发明授权

US07339238B2 Semiconductor device including a capacitance 失效
标题翻译：包括电容的半导体装置
公开(公告)号：US07339238B2
公开(公告)日：2008-03-04
申请号：US11510582
申请日：2006-08-28
申请人： Shigenobu Maeda , Takashi Ipposhi , Yuuichi Hirano
发明人： Shigenobu Maeda , Takashi Ipposhi , Yuuichi Hirano
IPC分类号： H01L29/76
CPC分类号： H01L21/84 , H01L27/0629 , H01L27/0808 , H01L27/0811 , H01L27/1203 , H01L29/66181 , H01L29/66545 , H01L29/94
摘要： It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer portion of the SOI layer (171) with a part of the SOI layer (171) remaining as a P− well region (169). Consequently, an isolation (partial isolation) structure is obtained. An N+ diffusion region (168) is formed in the SOI layer (171) between the isolating oxide films (167a) and (167b) and a P+ diffusion region (170) is formed in the SOI layer (171) between the isolating oxide films (167b) and (167c). Consequently, there is obtained a junction type variable capacitance (C23) having a PN junction surface of the P− well region (169) provided under the isolating oxide film (167b) and the N+ diffusion region (168).
摘要翻译：本发明的目的是获得包括具有大Q值的电容的半导体器件。在包括支撑衬底（165），掩埋氧化膜（166）和SOI层（171）的SOI衬底中，在SOI的上层部分中选择性地形成隔离氧化膜167（167a至167c）层（171）与SOI层（171）的一部分保持为阱区（169）。因此，获得隔离（部分隔离）结构。在隔离氧化膜（167a）和（167b）之间的SOI层（171）中形成有N + +扩散区（168）和P + 区域（170）形成在隔离氧化膜（167b）和（167c）之间的SOI层（171）中。因此，获得了具有设置在隔离氧化膜（167b）下面的P阱区域（169）的PN结表面的结型可变电容（C23）和N

5. 发明授权

US07303950B2 Semiconductor device, method of manufacturing same and method of designing same 有权
标题翻译：半导体装置及其制造方法及其设计方法
公开(公告)号：US07303950B2
公开(公告)日：2007-12-04
申请号：US11034938
申请日：2005-01-14
申请人： Yasuo Yamaguchi , Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Takuji Matsumoto , Shoichi Miyamoto
发明人： Yasuo Yamaguchi , Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Takuji Matsumoto , Shoichi Miyamoto
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L27/1203
摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.
摘要翻译：在其之间形成的具有阱区的部分氧化物膜（31）将SOI层（3）中的晶体管形成区域彼此隔离。在部分氧化膜（31）的下部形成p型阱区（11），其将NMOS晶体管彼此隔离，并且在部分氧化膜（31）的一部分下面形成n型阱区（12）），其将PMOS晶体管彼此隔离。 p型阱区（11）和n型阱区（12）在部分氧化膜（31）的一部分下方并排地形成，其提供NMOS和PMOS晶体管之间的隔离。身体区域与与其相邻的井区域（11）接触。形成在层间绝缘膜（4）上的互连层通过设置在层间绝缘膜（4）中的主体接触部电连接到体区。具有SOI结构的半导体器件减少浮置衬底效应。

6. 发明授权

US06452249B1 Inductor with patterned ground shield 有权
标题翻译：带有图案接地屏蔽的电感器
公开(公告)号：US06452249B1
公开(公告)日：2002-09-17
申请号：US09688812
申请日：2000-10-17
申请人： Shigenobu Maeda , Yasuo Yamaguchi , Yuuichi Hirano , Takashi Ipposhi , Takuji Matsumoto
发明人： Shigenobu Maeda , Yasuo Yamaguchi , Yuuichi Hirano , Takashi Ipposhi , Takuji Matsumoto
IPC分类号： H01L2900
CPC分类号： H01L23/5227 , H01L21/28518 , H01L21/84 , H01L23/645 , H01L27/0688 , H01L27/08 , H01L27/1203 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having an inductor is provided. In an RF circuit portion (RP), a region in an SOI layer (3) corresponding to a region in which a spiral inductor (SI) is provided is divided into a plurality of SOI regions (21) by a plurality of trench isolation oxide films (11). The trench isolation oxide films (11) are formed by filling trenches extending from the surface of the SOI layer (3) to the surface of a buried oxide film (2) with a silicon oxide film, and completely electrically isolate the SOI regions (21) from each other. The trench isolation oxide films (11) have a predetermined width and are shaped to extend substantially perpendicularly to the surface of the buried oxide film (2). The semiconductor device is capable of reducing electrostatically induced power dissipation and electromagnetically induced power dissipation, and preventing the structure and manufacturing steps thereof from becoming complicated.
摘要翻译：提供具有电感器的半导体器件。在RF电路部分（RP）中，与设置有螺旋电感器（SI）的区域对应的SOI层（3）中的区域被多个沟槽隔离氧化物（21）分成多个SOI区域电影（11）。沟槽隔离氧化膜（11）通过用氧化硅膜填充从SOI层（3）的表面延伸到掩埋氧化膜（2）的表面的沟槽而形成，并将SOI区域（21 ）彼此。沟槽隔离氧化物膜（11）具有预定的宽度并且被成形为基本上垂直于掩埋氧化膜（2）的表面延伸。半导体器件能够降低静电感应功率耗散和电磁感应功率消耗，并且防止其结构和制造步骤变得复杂。

7. 发明申请

US20070007595A1 Semiconductor device with effective heat-radiation 审中-公开
标题翻译：具有有效散热的半导体器件
公开(公告)号：US20070007595A1
公开(公告)日：2007-01-11
申请号：US11520640
申请日：2006-09-14
申请人： Yuuichi Hirano , Shigenobu Maeda , Takuji Matsumoto , Takashi Ipposhi , Shigeto Maegawa
发明人： Yuuichi Hirano , Shigenobu Maeda , Takuji Matsumoto , Takashi Ipposhi , Shigeto Maegawa
IPC分类号： H01L27/12
CPC分类号： H01L23/481 , H01L21/8221 , H01L21/84 , H01L27/0688 , H01L27/1203 , H01L29/78639 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device has a silicon layer (SOI layer) (12) formed through a silicon oxide film (11) on a support substrate (10). A transistor (T1) is formed in the SOI layer (12). The wiring (17a) is connected with a source of the transistor (T1) through a contact plug (15a). A back metal (18) is formed on an under surface (back surface) of the support substrate (10) and said back metal (18) is connected with the wiring (17a) through a heat radiating plug (16). The contact plug (15a), the heat radiating plug (16) the wiring (17a) and the back metal (18) is made of a metal such as aluminum, tungsten and so on which has a higher thermal conductivity than that of the silicon oxide film (11) and the support substrate (10).
摘要翻译：半导体器件具有通过支撑衬底（10）上的氧化硅膜（11）形成的硅层（SOI层）（12）。在SOI层（12）中形成晶体管（T 1）。布线（17a）通过接触插塞（15A）与晶体管（T 1）的源极连接。背衬金属（18）形成在支撑基板（10）的下表面（背面）上，所述背金属（18）通过散热塞（16）与布线（17a）连接。接触塞（15A），散热塞（16），布线（17a）和背金属（18）由诸如铝，钨等的金属制成，其具有比氧化硅膜（11）和支撑基板（10）。

8. 发明授权

US07112835B2 Semiconductor device including a capacitance 有权
标题翻译：包括电容的半导体装置
公开(公告)号：US07112835B2
公开(公告)日：2006-09-26
申请号：US10995193
申请日：2004-11-24
申请人： Shigenobu Maeda , Takashi Ipposhi , Yuuichi Hirano
发明人： Shigenobu Maeda , Takashi Ipposhi , Yuuichi Hirano
IPC分类号： H01L29/93
CPC分类号： H01L21/84 , H01L27/0629 , H01L27/0808 , H01L27/0811 , H01L27/1203 , H01L29/66181 , H01L29/66545 , H01L29/94
摘要： It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer portion of the SOI layer (171) with a part of the SOI layer (171) remaining as a P− well region (169). Consequently, an isolation (partial isolation) structure is obtained. An N+ diffusion region (168) is formed in the SOI layer (171) between the isolating oxide films (167a) and (167b) and a P+ diffusion region (170) is formed in the SOI layer (171) between the isolating oxide films (167b) and (167c). Consequently, there is obtained a junction type variable capacitance (C23) having a PN junction surface of the P− well region (169) provided under the isolating oxide film (167b) and the N+ diffusion region (168).
摘要翻译：本发明的目的是获得包括具有大Q值的电容的半导体器件。在包括支撑衬底（165），掩埋氧化膜（166）和SOI层（171）的SOI衬底中，在SOI的上层部分中选择性地形成隔离氧化膜167（167a至167c）层（171）与SOI层（171）的一部分保持为阱区（169）。因此，获得隔离（部分隔离）结构。在隔离氧化膜（167a）和（167b）之间的SOI层（171）中形成有N + +扩散区（168）和P + 区域（170）形成在隔离氧化膜（167b）和（167c）之间的SOI层（171）中。因此，获得了具有设置在隔离氧化膜（167b）下面的P阱区域（169）的PN结表面的结型可变电容（C23）和N

9. 发明申请

US20050087779A1 Semiconductor device including a capacitance 有权
标题翻译：包括电容的半导体装置
公开(公告)号：US20050087779A1
公开(公告)日：2005-04-28
申请号：US10995193
申请日：2004-11-24
申请人： Shigenobu Maeda , Takashi Ipposhi , Yuuichi Hirano
发明人： Shigenobu Maeda , Takashi Ipposhi , Yuuichi Hirano
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L21/8238 , H01L27/06 , H01L27/08 , H01L27/092 , H01L29/786 , H01L29/94 , H01L29/76 , H01L21/336
CPC分类号： H01L21/84 , H01L27/0629 , H01L27/0808 , H01L27/0811 , H01L27/1203 , H01L29/66181 , H01L29/66545 , H01L29/94
摘要： It is an object to obtain a semiconductor device including a capacitance having a great Q-value. In an SOI substrate comprising a support substrate (165), a buried oxide film (166) and an SOI layer (171), an isolating oxide film 167 (167a to 167c) is selectively formed in an upper layer portion of the SOI layer (171) with a part of the SOI layer (171) remaining as a P− well region (169). Consequently, an isolation (partial isolation) structure is obtained. An N+ diffusion region (168) is formed in the SOI layer (171) between the isolating oxide films (167a) and (167b) and a P+ diffusion region (170) is formed in the SOI layer (171) between the isolating oxide films (167b) and (167c). Consequently, there is obtained a junction type variable capacitance (C23) having a PN junction surface of the P− well region (169) provided under the isolating oxide film (167b) and the N+ diffusion region (168).
摘要翻译：本发明的目的是获得包括具有大Q值的电容的半导体器件。在包括支撑衬底（165），掩埋氧化膜（166）和SOI层（171）的SOI衬底中，在SOI的上层部分中选择性地形成隔离氧化膜167（167a至167c）层（171）与SOI层（171）的一部分保持为阱区（169）。因此，获得隔离（部分隔离）结构。在隔离氧化膜（167a）和（167b）之间的SOI层（171）中形成有N + +扩散区（168）和P + 区域（170）形成在隔离氧化膜（167b）和（167c）之间的SOI层（171）中。因此，获得了具有设置在隔离氧化膜（167b）下面的P阱区域（169）的PN结表面的结型可变电容（C23）和N

10. 发明授权

US07741679B2 Semiconductor device, method of manufacturing same and method of designing same 有权
标题翻译：半导体装置及其制造方法及其设计方法
公开(公告)号：US07741679B2
公开(公告)日：2010-06-22
申请号：US11866693
申请日：2007-10-03
申请人： Yasuo Yamaguchi , Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Takuji Matsumoto , Shoichi Miyamoto
发明人： Yasuo Yamaguchi , Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Takuji Matsumoto , Shoichi Miyamoto
IPC分类号： H01L23/62
CPC分类号： H01L21/84 , H01L27/1203
摘要： A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type well region is formed beneath part of the partial oxide film which isolates PMOS transistors from each other. The p-type well region and the n-type well region are formed in side-by-side relation beneath part of the partial oxide film which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region adjacent thereto. An interconnect layer formed on an interlayer insulation film is electrically connected to the body region through a body contact provided in the interlayer insulation film. A semiconductor device having an SOI structure reduces a floating-substrate effect.
摘要翻译：在其之间形成的具有阱区的部分氧化膜彼此隔离SOI层中的晶体管形成区域。在部分氧化膜的下部形成有p型阱区，其将NMOS晶体管彼此隔离，并且在部分氧化膜的下部形成n型阱区，其将PMOS晶体管彼此隔离。 p型阱区域和n型阱区域在部分氧化膜的一部分下方并排地形成，其提供NMOS和PMOS晶体管之间的隔离。身体区域与与其相邻的井区域接触。形成在层间绝缘膜上的互连层通过设置在层间绝缘膜中的体接触电连接到体区。具有SOI结构的半导体器件减少浮置衬底效应。

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