专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20050184342A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20050184342A1
公开(公告)日：2005-08-25
申请号：US11108843
申请日：2005-04-19
申请人： Yuuichi Hirano , Shigeto Maegawa , Toshiaki Iwamatsu , Takuji Matsumoto , Shigenobu Maeda , Yasuo Yamaguchi
发明人： Yuuichi Hirano , Shigeto Maegawa , Toshiaki Iwamatsu , Takuji Matsumoto , Shigenobu Maeda , Yasuo Yamaguchi
IPC分类号： H01L21/762 , H01L21/3205 , H01L21/76 , H01L21/822 , H01L21/8238 , H01L21/84 , H01L23/52 , H01L27/04 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/786 , H01L21/336 , H01L21/00 , H01L21/331 , H01L27/01 , H01L31/0392
CPC分类号： H01L27/1203 , H01L21/84
摘要： An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.
摘要翻译：在硅层（4）的上表面中选择性地形成部分沟槽型隔离绝缘膜（5）。电源线（21）形成在隔离绝缘膜（5）的上方。在电源线（21）的下方，在隔离绝缘膜（5）上形成到达绝缘膜（3）的上表面的完全隔离部（23）。换句话说，半导体器件包括完全隔离绝缘膜，其形成为从硅层（4）的上表面延伸并到达电源线（21）下方的绝缘膜（3）的上表面）。利用这种结构，可以获得能够抑制由电源线的电位变化引起的体区的电位变化的半导体器件。

2. 发明申请

US20050156242A1 Semiconductor device, method of manufacturing same and method of designing same 有权
公开(公告)号：US20050156242A1
公开(公告)日：2005-07-21
申请号：US11034938
申请日：2005-01-14
申请人： Yasuo Yamaguchi , Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Takuji Matsumoto , Shoichi Miyamoto
发明人： Yasuo Yamaguchi , Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Takuji Matsumoto , Shoichi Miyamoto
IPC分类号： H01L21/762 , H01L21/331 , H01L21/8238 , H01L21/84 , H01L27/01 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/786 , H01L31/00
CPC分类号： H01L21/84 , H01L27/1203
摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

3. 发明授权

US06953979B1 Semiconductor device, method of manufacturing same and method of designing same 失效
标题翻译：半导体装置及其制造方法及其设计方法
公开(公告)号：US06953979B1
公开(公告)日：2005-10-11
申请号：US09466934
申请日：1999-12-20
申请人： Yasuo Yamaguchi , Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Takuji Matsumoto , Shoichi Miyamoto
发明人： Yasuo Yamaguchi , Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Takuji Matsumoto , Shoichi Miyamoto
IPC分类号： H01L21/762 , H01L21/331 , H01L21/8238 , H01L21/84 , H01L27/01 , H01L27/08 , H01L27/092 , H01L27/12 , H01L29/786 , H01L31/00
CPC分类号： H01L21/84 , H01L27/1203
摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.
摘要翻译：在其之间形成的具有阱区的部分氧化物膜（31）将SOI层（3）中的晶体管形成区域彼此隔离。在部分氧化膜（31）的下部形成p型阱区（11），其将NMOS晶体管彼此隔离，并且在部分氧化膜（31）的一部分下方形成n型阱区（12）），其将PMOS晶体管彼此隔离。 p型阱区（11）和n型阱区（12）在部分氧化膜（31）的下部并排形成，其提供NMOS和PMOS晶体管之间的隔离。身体区域与与其相邻的井区域（11）接触。形成在层间绝缘膜（4）上的互连层通过设置在层间绝缘膜（4）中的主体接触部电连接到体区。具有SOI结构的半导体器件减少浮置衬底效应。

4. 发明授权

US06882006B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06882006B2
公开(公告)日：2005-04-19
申请号：US10188103
申请日：2002-07-03
申请人： Shigenobu Maeda , Yasuo Yamaguchi , Hirotada Kuriyama , Shigeto Maegawa
发明人： Shigenobu Maeda , Yasuo Yamaguchi , Hirotada Kuriyama , Shigeto Maegawa
IPC分类号： H01L21/768 , H01L21/8242 , H01L27/092 , H01L27/10 , H01L27/108 , H01L27/11 , H01L27/12 , H01L29/78 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/092 , H01L27/10823 , H01L27/10841 , H01L27/1104 , H01L27/1203 , H01L29/66666 , H01L29/7827
摘要： A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. The gate electrode is covered with a second interlayer insulating film. A contact hole for exposing a part of the surface of the source region is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is provided on the surface of the source region in contact therewith up to the lower surface of the gate electrode. A channel semiconductor layer is provided on the surface of the first semiconductor layer up to the upper surface of the gate electrode. A second semiconductor layer of a first conductivity type serving as a drain region is provided on the channel semiconductor layer.
摘要翻译：可以获得占据小面积的场效应晶体管和使用其的半导体器件。栅电极设置在基板上，源极区域之间插入有第一层间绝缘膜。栅电极被第二层间绝缘膜覆盖。提供用于暴露源区域的一部分表面的接触孔，以穿透第一层间绝缘膜，栅电极和第二层间绝缘膜。接触孔的侧壁表面被栅极绝缘膜覆盖。第一导电类型的第一半导体层设置在与其接触的源极区域的表面上，直到栅电极的下表面。沟道半导体层设置在第一半导体层的表面上直到栅电极的上表面。在沟道半导体层上设置有用作漏极区的第一导电类型的第二半导体层。

5. 发明授权

US07439587B2 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07439587B2
公开(公告)日：2008-10-21
申请号：US11677956
申请日：2007-02-22
申请人： Yuuichi Hirano , Shigeto Maegawa , Toshiaki Iwamatsu , Takuji Matsumoto , Shigenobu Maeda , Yasuo Yamaguchi
发明人： Yuuichi Hirano , Shigeto Maegawa , Toshiaki Iwamatsu , Takuji Matsumoto , Shigenobu Maeda , Yasuo Yamaguchi
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L27/1203 , H01L21/84
摘要： An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.
摘要翻译：在硅层（4）的上表面中选择性地形成部分沟槽型隔离绝缘膜（5）。电源线（21）形成在隔离绝缘膜（5）的上方。在电源线（21）的下方，在隔离绝缘膜（5）上形成到达绝缘膜（3）的上表面的完全隔离部（23）。换句话说，半导体器件包括完全隔离绝缘膜，其形成为从硅层（4）的上表面延伸并到达电源线（21）下方的绝缘膜（3）的上表面）。利用这种结构，可以获得能够抑制由电源线的电位变化引起的体区的电位变化的半导体器件。

6. 发明申请

US20070132028A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
公开(公告)号：US20070132028A1
公开(公告)日：2007-06-14
申请号：US11677951
申请日：2007-02-22
申请人： Yuuichi Hirano , Shigeto Maegawa , Toshiaki Iwamatsu , Takuji Matsumoto , Shigenobu Maeda , Yasuo Yamaguchi
发明人： Yuuichi Hirano , Shigeto Maegawa , Toshiaki Iwamatsu , Takuji Matsumoto , Shigenobu Maeda , Yasuo Yamaguchi
IPC分类号： H01L27/12
CPC分类号： H01L27/1203 , H01L21/84
摘要： An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.

7. 发明授权

US06190967B1 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06190967B1
公开(公告)日：2001-02-20
申请号：US09166584
申请日：1998-10-06
申请人： Shigenobu Maeda , Shigeto Maegawa , Yasuo Yamaguchi
发明人： Shigenobu Maeda , Shigeto Maegawa , Yasuo Yamaguchi
IPC分类号： H01L21336
CPC分类号： H01L27/105
摘要： The semiconductor device includes a silicon substrate, field effect transistors, a flash memory and a separating portion. A plurality of field effect transistors are formed on semiconductor substrate. A flash memory is formed on semiconductor substrate. Separating portion includes a separation electrode. Separating portion electrically separates the plurality of field effect transistors from each other. Separating portion is formed insulated on silicon substrate. Flash memory includes a floating gate electrode and a control gate electrode. Floating gate electrode is formed insulated on silicon substrate. Control gate electrode is formed insulated on floating gate electrode. Separation electrode and floating gate electrode have approximately the same thickness.
摘要翻译：半导体器件包括硅衬底，场效应晶体管，闪存和分离部分。在半导体衬底上形成多个场效应晶体管。在半导体衬底上形成闪速存储器。分离部分包括分离电极。分离部分将多个场效应晶体管彼此电分离。分离部分在硅衬底上形成绝缘。闪存包括浮栅电极和控制栅电极。浮栅电极在硅衬底上形成绝缘。控制栅电极在浮栅电极上形成绝缘。分离电极和浮栅电极具有大致相同的厚度。

8. 发明授权

US5994735A Semiconductor device having a vertical surround gate metal-oxide semiconductor field effect transistor, and manufacturing method thereof 失效
标题翻译：具有垂直环绕栅极金属氧化物半导体场效应晶体管的半导体器件及其制造方法
公开(公告)号：US5994735A
公开(公告)日：1999-11-30
申请号：US582810
申请日：1996-01-04
申请人： Shigenobu Maeda , Yasuo Yamaguchi , Hirotada Kuriyama , Shigeto Maegawa
发明人： Shigenobu Maeda , Yasuo Yamaguchi , Hirotada Kuriyama , Shigeto Maegawa
IPC分类号： H01L21/768 , H01L21/8242 , H01L27/092 , H01L27/10 , H01L27/108 , H01L27/11 , H01L27/12 , H01L29/78 , H01L29/76 , H01L27/01 , H01L29/94
CPC分类号： H01L27/092 , H01L27/10823 , H01L27/10841 , H01L27/1104 , H01L27/1203 , H01L29/66666 , H01L29/7827
摘要： A field effect transistor occupying a small area and a semiconductor device using the same can be obtained. A gate electrode is provided on a substrate on which a source region is provided with a first interlayer insulating film interposed therebetween. The gate electrode is covered with a second interlayer insulating film. A contact hole for exposing a part of the surface of the source region is provided so as to penetrate through the first interlayer insulating film, the gate electrode, and the second interlayer insulating film. A sidewall surface of the contact hole is covered with a gate insulating film. A first semiconductor layer of a first conductivity type is provided on the surface of the source region in contact therewith up to the lower surface of the gate electrode. A channel semiconductor layer is provided on the surface of the first semiconductor layer up to the upper surface of the gate electrode. A second semiconductor layer of a first conductivity type serving as a drain region is provided on the channel semiconductor layer.
摘要翻译：可以获得占据小面积的场效应晶体管和使用其的半导体器件。栅电极设置在基板上，源极区域之间插入有第一层间绝缘膜。栅电极被第二层间绝缘膜覆盖。提供用于暴露源区域的一部分表面的接触孔，以穿透第一层间绝缘膜，栅电极和第二层间绝缘膜。接触孔的侧壁表面被栅极绝缘膜覆盖。第一导电类型的第一半导体层设置在与其接触的源极区域的表面上，直到栅电极的下表面。沟道半导体层设置在第一半导体层的表面上直到栅电极的上表面。在沟道半导体层上设置有用作漏极区的第一导电类型的第二半导体层。

9. 发明授权

US07482658B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07482658B2
公开(公告)日：2009-01-27
申请号：US11677951
申请日：2007-02-22
申请人： Yuuichi Hirano , Shigeto Maegawa , Toshiaki Iwamatsu , Takuji Matsumoto , Shigenobu Maeda , Yasuo Yamaguchi
发明人： Yuuichi Hirano , Shigeto Maegawa , Toshiaki Iwamatsu , Takuji Matsumoto , Shigenobu Maeda , Yasuo Yamaguchi
IPC分类号： H01L21/00
CPC分类号： H01L27/1203 , H01L21/84
摘要： An isolation insulating film (5) of partial-trench type is selectively formed in an upper surface of a silicon layer (4). A power supply line (21) is formed above the isolation insulating film (5). Below the power supply line (21), a complete isolation portion (23) reaching an upper surface of an insulating film (3) is formed in the isolation insulating film (5). In other words, a semiconductor device comprises a complete-isolation insulating film which is so formed as to extend from the upper surface of the silicon layer (4) and reach the upper surface of insulating film (3) below the power supply line (21). With this structure, it is possible to obtain the semiconductor device capable of suppressing variation in potential of a body region caused by variation in potential of the power supply line.
摘要翻译：在硅层（4）的上表面中选择性地形成部分沟槽型隔离绝缘膜（5）。电源线（21）形成在隔离绝缘膜（5）的上方。在电源线（21）的下方，在隔离绝缘膜（5）上形成到达绝缘膜（3）的上表面的完全隔离部（23）。换句话说，半导体器件包括完全隔离绝缘膜，其形成为从硅层（4）的上表面延伸并到达电源线（21）下方的绝缘膜（3）的上表面）。利用这种结构，可以获得能够抑制由电源线的电位变化引起的体区的电位变化的半导体器件。

10. 发明授权

US07303950B2 Semiconductor device, method of manufacturing same and method of designing same 有权
标题翻译：半导体装置及其制造方法及其设计方法
公开(公告)号：US07303950B2
公开(公告)日：2007-12-04
申请号：US11034938
申请日：2005-01-14
申请人： Yasuo Yamaguchi , Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Takuji Matsumoto , Shoichi Miyamoto
发明人： Yasuo Yamaguchi , Shigeto Maegawa , Takashi Ipposhi , Toshiaki Iwamatsu , Shigenobu Maeda , Yuuichi Hirano , Takuji Matsumoto , Shoichi Miyamoto
IPC分类号： H01L21/8238
CPC分类号： H01L21/84 , H01L27/1203
摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.
摘要翻译：在其之间形成的具有阱区的部分氧化物膜（31）将SOI层（3）中的晶体管形成区域彼此隔离。在部分氧化膜（31）的下部形成p型阱区（11），其将NMOS晶体管彼此隔离，并且在部分氧化膜（31）的一部分下面形成n型阱区（12）），其将PMOS晶体管彼此隔离。 p型阱区（11）和n型阱区（12）在部分氧化膜（31）的一部分下方并排地形成，其提供NMOS和PMOS晶体管之间的隔离。身体区域与与其相邻的井区域（11）接触。形成在层间绝缘膜（4）上的互连层通过设置在层间绝缘膜（4）中的主体接触部电连接到体区。具有SOI结构的半导体器件减少浮置衬底效应。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式