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1. 发明授权

US06777997B2 Semiconductor integrated circuit and a burn-in method thereof 失效
标题翻译：半导体集成电路及其老化方法
公开(公告)号：US06777997B2
公开(公告)日：2004-08-17
申请号：US10309183
申请日：2002-12-04
申请人： Shigemitsu Tahara , Daisuke Katagiri , Takeshi Shimanuki , Masashi Oshiba
发明人： Shigemitsu Tahara , Daisuke Katagiri , Takeshi Shimanuki , Masashi Oshiba
IPC分类号： H03L500
CPC分类号： H03K19/018585 , H03K19/01855
摘要： The present invention realizes higher-speed external output operation synchronized with a clock signal from the viewpoint of prevention of output operation delay due to a level shift circuit and maintenance of a high breakdown voltage of an output buffer. A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than a breakdown voltage of the first circuit, and operation voltages of the first and second circuits can be made equal to each other or different from each other. The second circuit has a plurality of level shift circuits capable of shifting the level of an output of the first circuit in accordance with an operation voltage of the second circuit, a plurality of external output buffers receiving outputs of the level shift circuits, bypasses for bypassing an input of a predetermined level shift circuit to an input of a predetermined external output buffer, and a selecting circuit for selecting connection of either the predetermined level shift circuit or a bypass to an input of the predetermined external output buffer. In a use form in which the first and second circuits operate with a low voltage, the bypass is selected. In high-voltage operation and burn-in, the level shift circuits are selected.
摘要翻译：从防止由于电平移位电路的输出操作延迟和维持输出缓冲器的高击穿电压的观点来看，本发明实现了与时钟信号同步的更高速的外部输出操作。半导体集成电路包括具有比第一电路的击穿电压高的击穿电压的第一电路和第二电路，并且可以使第一和第二电路的操作电压彼此相等或不同。第二电路具有多个电平移位电路，能够根据第二电路的工作电压来移动第一电路的输出电平，接收电平移位电路的输出的多个外部输出缓冲器，用于旁路的旁路将预定电平移位电路输入到预定的外部输出缓冲器的输入端，以及选择电路，用于选择预定电平移位电路或旁路中的任一者与预定外部输出缓冲器的输入端的连接。在第一和第二电路以低电压工作的使用形式中，选择旁路。在高压运行和老化期间，选择电平移位电路。

2. 发明授权

US07109779B2 Semiconductor integrated circuit and a burn-in method thereof 失效
标题翻译：半导体集成电路及其老化方法
公开(公告)号：US07109779B2
公开(公告)日：2006-09-19
申请号：US11153355
申请日：2005-06-16
申请人： Shigemitsu Tahara , Daisuke Katagiri , Takeshi Shimanuki , Masashi Oshiba
发明人： Shigemitsu Tahara , Daisuke Katagiri , Takeshi Shimanuki , Masashi Oshiba
IPC分类号： H03L5/00
CPC分类号： H03K19/018585 , H03K19/01855
摘要： A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than that of the first circuit. Operation voltages of the first and second circuits can be made equal to or different from each other. The second circuit has a level shift circuit for shifting the level of an output signal of the first circuit in accordance with an operation voltage of the second circuit, an external output buffer having an input that can receive, selectively, an output signal of the level shift circuit or an input signal that bypasses the level shift circuit. When the first and second circuits operate with a low voltage, bypass is selected. In high-voltage operation and burn-in, the level shift circuit is selected.
摘要翻译：半导体集成电路包括具有高于第一电路的击穿电压的第一电路和第二电路。可以使第一和第二电路的工作电压彼此相等或不同。第二电路具有电平移位电路，用于根据第二电路的操作电压来移位第一电路的输出信号的电平，外部输出缓冲器具有可以选择性地接收电平的输出信号的输入移位电路或旁路电平移位电路的输入信号。当第一和第二电路以低电压工作时，选择旁路。在高压运行和老化期间，选择电平移位电路。

3. 发明申请

US20050231262A1 Semiconductor integrated circuit and a burn-in method thereof 失效
标题翻译：半导体集成电路及其老化方法
公开(公告)号：US20050231262A1
公开(公告)日：2005-10-20
申请号：US11153355
申请日：2005-06-16
申请人： Shigemitsu Tahara , Daisuke Katagiri , Takeshi Shimanuki , Masashi Oshiba
发明人： Shigemitsu Tahara , Daisuke Katagiri , Takeshi Shimanuki , Masashi Oshiba
IPC分类号： G01R31/30 , G01R31/28 , G01R31/316 , H01L21/822 , H01L27/04 , H03K19/0175 , H03K19/0185 , H03L5/00
CPC分类号： H03K19/018585 , H03K19/01855
摘要： A semiconductor integrated circuit includes a first circuit and a second circuit having a breakdown voltage higher than that of the first circuit. Operation voltages of the first and second circuits can be made equal to or different from each other. The second circuit has a level shift circuit for shifting the level of an output signal of the first circuit in accordance with an operation voltage of the second circuit, an external output buffer having an input that can receive, selectively, an output signal of the level shift circuit or an input signal that bypasses the level shift circuit. When the first and second circuits operate with a low voltage, bypass is selected. In high-voltage operation and burn-in, the level shift circuit is selected.
摘要翻译：半导体集成电路包括具有高于第一电路的击穿电压的第一电路和第二电路。可以使第一和第二电路的工作电压彼此相等或不同。第二电路具有电平移位电路，用于根据第二电路的操作电压来移位第一电路的输出信号的电平，外部输出缓冲器具有可以选择性地接收电平的输出信号的输入移位电路或旁路电平移位电路的输入信号。当第一和第二电路以低电压工作时，选择旁路。在高压运行和老化期间，选择电平移位电路。

4. 发明授权

US07447894B2 Microcomputer having a nonvolatile memory which stores a plurality of BIOSes 失效
标题翻译：具有存储多个BIOS的非易失性存储器的微计算机
公开(公告)号：US07447894B2
公开(公告)日：2008-11-04
申请号：US10901344
申请日：2004-07-29
申请人： Masashi Oshiba , Yoshiaki Sato , Kentaro Yamakawa , Yoko Yamaki , Hiroshi Kishi
发明人： Masashi Oshiba , Yoshiaki Sato , Kentaro Yamakawa , Yoko Yamaki , Hiroshi Kishi
IPC分类号： G06F9/22
CPC分类号： G06F1/24
摘要： A microcomputer capable of reducing a board area, enhancing the security, and improving the usability is provided. A microcomputer to be used in a notebook PC is disclosed, in which programs of a keyboard/power management BIOS and a system BIOS are stored in a built-in flash memory ROM. In order to set read (R)/write (W) protect to the BIOSes stored in the flash memory ROM, a read/write protect setting register is provided, and at initial setting after the release of reset, flags of R/W permission, R permission/W prohibition, W permission/R prohibition, and R/W prohibition are set to this register by a central processing unit CPU. By doing so, it becomes possible to achieve protection such as the prevention of error writing of the BIOS and the like between a host machine and the flash memory ROM via a LPC bus.
摘要翻译：提供了能够减少电路板面积，提高安全性并提高可用性的微型计算机。公开了一种用于笔记本电脑的微计算机，其中键盘/电源管理BIOS和系统BIOS的程序存储在内置的闪存ROM中。为了将存储在闪存ROM中的BIOS设置为读（R）/写（W）保护，提供读/写保护设置寄存器，并且在复位释放之后的初始设置，R / W许可的标志，R权限/ W禁止，W权限/ R禁止和R / W禁止由中央处理单元CPU设置到该寄存器。通过这样做，可以通过LPC总线实现诸如防止主机和闪存ROM之间的BIOS等的错误写入的保护。

5. 发明申请

US20050050312A1 Microcomputer 失效
标题翻译：微电脑
公开(公告)号：US20050050312A1
公开(公告)日：2005-03-03
申请号：US10901344
申请日：2004-07-29
申请人： Masashi Oshiba , Yoshiaki Sato , Kentaro Yamakawa , Yoko Yamaki , Hiroshi Kishi
发明人： Masashi Oshiba , Yoshiaki Sato , Kentaro Yamakawa , Yoko Yamaki , Hiroshi Kishi
IPC分类号： G06F12/14 , G06F11/00 , G06F15/177 , G06F15/78
CPC分类号： G06F1/24
摘要： A microcomputer capable of reducing a board area, enhancing the security, and improving the usability is provided. A microcomputer to be used in a notebook PC is disclosed, in which programs of a keyboard/power management BIOS and a system BIOS are stored in a built-in flash memory ROM. In order to set read (R)/write (W) protect to the BIOSes stored in the flash memory ROM, a read/write protect setting register is provided, and at initial setting after the release of reset, flags of R/W permission, R permission/W prohibition, W permission/R prohibition, and R/W prohibition are set to this register by a central processing unit CPU. By doing so, it becomes possible to achieve protection such as the prevention of error writing of the BIOS and the like between a host machine and the flash memory ROM via a LPC bus.
摘要翻译：提供了能够减少电路板面积，提高安全性并提高可用性的微型计算机。公开了一种用于笔记本电脑的微计算机，其中键盘/电源管理BIOS和系统BIOS的程序存储在内置的闪存ROM中。为了将存储在闪存ROM中的BIOS设置为读（R）/写（W）保护，提供读/写保护设置寄存器，并且在复位释放之后的初始设置，R / W许可的标志，R权限/ W禁止，W权限/ R禁止和R / W禁止由中央处理单元CPU设置到该寄存器。通过这样做，可以通过LPC总线实现诸如防止主机和闪存ROM之间的BIOS等的错误写入的保护。

6. 发明申请

US20070133280A1 Semiconductor integrated circuit apparatus and electronic system 审中-公开
标题翻译：半导体集成电路设备和电子系统
公开(公告)号：US20070133280A1
公开(公告)日：2007-06-14
申请号：US10583778
申请日：2004-10-08
申请人： Masashi Oshiba , Hiroshi Kishi , Yoshiaki Sato , Yoko Yamaki , Kentaro Yamakawa
发明人： Masashi Oshiba , Hiroshi Kishi , Yoshiaki Sato , Yoko Yamaki , Kentaro Yamakawa
IPC分类号： G11C16/04
CPC分类号： G11C16/22 , G06F12/1433
摘要： A flash memory is provided with a protect area PA in which reading of a specific block is prohibited. A RAM to be used as a work area of a program is provided with a protect area PA1 in which reading of a specific block is prohibited. A bus state controller 3 compares a value of a program counter and a value of an address signal to prohibit reading in areas other than the protect area PA in the flash memory and to prohibit reading of data of protect area PA1 in the RAM other than reading from the protect area PA of the flash memory. For instance, when a user reads data of the protect area PA from a user access area to which the user can access, senseless data such as H'FFFF are output from the bus state controller 3 via a data bus.
摘要翻译：闪存具有保护区域PA，其中禁止读取特定块。用作程序的工作区域的RAM设置有禁止特定块的读取的保护区域PA1。总线状态控制器3比较程序计数器的值和地址信号的值，以禁止在闪速存储器中的保护区域PA之外的区域中的读取，并且禁止读取除了读取之外的RAM中的保护区域PA1的数据从闪存的保护区PA。例如，当用户从用户可以访问的用户访问区域读取保护区域PA的数据时，经由数据总线从总线状态控制器3输出诸如H'FFFF之类的无意义数据。

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