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1. 发明授权

US06768183B2 Semiconductor device having bipolar transistors 失效
标题翻译：具有双极晶体管的半导体器件
公开(公告)号：US06768183B2
公开(公告)日：2004-07-27
申请号：US10125582
申请日：2002-04-19
申请人： Shigeki Takahashi , Satoshi Shiraki , Hiroaki Himi , Hiroyuki Ban , Osamu Seya
发明人： Shigeki Takahashi , Satoshi Shiraki , Hiroaki Himi , Hiroyuki Ban , Osamu Seya
IPC分类号： H01L2900
CPC分类号： H01L27/0826 , H01L27/0623
摘要： An NPN bipolar transistor and a PNP bipolar transistor are formed in a semiconductor substrate. The NPN bipolar transistor has a p type emitter region, a p type collector region and an n type base region and is formed in an NPN forming region. The PNP bipolar transistor has an n type emitter region, an n type collector region and a p type base region and is formed in a PNP forming region. Only one conductive type burying region is formed in at least one of the NPN forming region and the PNP forming region. A current that flows from the p type emitter region to the n type base region flows in the n type base region in a direction perpendicular to the substrate.
摘要翻译：在半导体衬底中形成NPN双极晶体管和PNP双极晶体管。 NPN双极晶体管具有p型发射极区域，p型集电极区域和n型基极区域，并且形成在NPN形成区域中。 PNP双极晶体管具有n型发射极区域，n型集电极区域和p型基极区域，并且形成在PNP形成区域中。在NPN形成区域和PNP形成区域的至少一个中仅形成一个导电型掩埋区域。从p型发射极区域流向n型基极区域的电流在与基板垂直的方向上流入n型基极区域。

2. 发明授权

US06573144B2 Method for manufacturing a semiconductor device having lateral MOSFET (LDMOS) 有权
公开(公告)号：US06573144B2
公开(公告)日：2003-06-03
申请号：US10210059
申请日：2002-08-02
申请人： Shigeki Takahashi , Hiroaki Himi , Satoshi Shiraki , Masatoshi Kato
发明人： Shigeki Takahashi , Hiroaki Himi , Satoshi Shiraki , Masatoshi Kato
IPC分类号： H01L21336
CPC分类号： H01L29/7824 , H01L27/0266 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L2924/0002 , H01L2924/00
摘要： In an LDMOS, an n-type region 6, which is formed to have a concentration higher than that of an n-type substrate 1 and whose concentration gradually increases from the n-type substrate 1 to an n+ type drain region 5, is disposed so as to surround the n+-type drain region 5. Further, a p+-type contact region 9 disposed adjacent to an n+-type source region 8 is formed so as to extend below the n+-type source region 8 so that a parasitic transistor formed by the n+-type source region 8, a p-type base region 7 and the n-type substrate 1 is hardly turned ON.

3. 发明授权

US06465839B2 Semiconductor device having lateral MOSFET (LDMOS) 有权
标题翻译：具有横向MOSFET（LDMOS）的半导体器件
公开(公告)号：US06465839B2
公开(公告)日：2002-10-15
申请号：US09827329
申请日：2001-04-06
申请人： Shigeki Takahashi , Hiroaki Himi , Satoshi Shiraki , Masatoshi Kato
发明人： Shigeki Takahashi , Hiroaki Himi , Satoshi Shiraki , Masatoshi Kato
IPC分类号： H01L29788
CPC分类号： H01L29/7824 , H01L27/0266 , H01L29/0847 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L2924/0002 , H01L2924/00
摘要： In an LDMOS, an n-type region 6, which is formed to have a concentration higher than that of an n-type substrate 1 and whose concentration gradually increases from the n-type substrate 1 to an n+ type drain region 5, is disposed so as to surround the n+-type drain region 5. Further, a p+-type contact region 9 disposed adjacent to an n+-type source region 8 is formed so as to extend below the n+-type source region 8 so that a parasitic transistor formed by the n+-type source region 8, a p-type base region 7 and the n-type substrate 1 is hardly turned ON.
摘要翻译：在LDMOS中，设置形成为具有比n型基板1的浓度高且浓度从n型基板1逐渐增加到n +型漏极区域5的n型区域6 以便围绕n +型漏极区域5.此外，与n +型源极区域8相邻配置的p +型接触区域9形成为在n +型源极区域8的下方延伸，使得寄生晶体管由n +型源极区域8形成，p型基极区域7和n型基板1几乎不导通。

4. 发明授权

US07838909B2 Semiconductor device with trench structure 有权
标题翻译：具有沟槽结构的半导体器件
公开(公告)号：US07838909B2
公开(公告)日：2010-11-23
申请号：US11528612
申请日：2006-09-28
申请人： Hiroaki Himi , Takashi Nakano , Shoji Mizuno
发明人： Hiroaki Himi , Takashi Nakano , Shoji Mizuno
IPC分类号： H01L27/10 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/7816 , H01L21/84 , H01L27/1203 , H01L29/0847 , H01L29/0878 , H01L29/7317 , H01L29/7824
摘要： A semiconductor device includes a common diffusion structure formed in each region of a substrate in which semiconductor components are formed. The diffusion structures are separated into sections by trenches to form semiconductor components. The trenches define sizes of the semiconductor components and isolate the semiconductor components from the surrounding area.
摘要翻译：半导体器件包括形成在其中形成半导体部件的衬底的每个区域中的公共扩散结构。扩散结构通过沟槽分成部分以形成半导体部件。沟槽限定半导体部件的尺寸并将半导体部件与周围区域隔离。

5. 发明授权

US07220654B2 Method for manufacturing semiconductor substrate 有权
公开(公告)号：US07220654B2
公开(公告)日：2007-05-22
申请号：US10716606
申请日：2003-11-20
申请人： Hiroaki Himi , Noriyuki Iwamori
发明人： Hiroaki Himi , Noriyuki Iwamori
IPC分类号： H01L21/76
CPC分类号： H01L21/6835 , H01L21/7624 , H01L21/76243 , H01L21/76251 , H01L21/76256 , H01L21/76264 , H01L2221/68363
摘要： An epitaxial layer is formed on a high-resistance semiconductor substrate containing interstitial oxygen at a high concentration, and then a heat treatment is performed to the semiconductor substrate at a high temperature in an oxidizing atmosphere. Accordingly, a stratiform region of SiO2 is formed by deposition at an interface between the epitaxial layer and the semiconductor substrate. As a result, an apparent SOI substrate for an SOI semiconductor device can be manufactured at a low cost.

6. 发明授权

US6064158A Electroluminescent display device 有权
标题翻译：电致发光显示装置
公开(公告)号：US6064158A
公开(公告)日：2000-05-16
申请号：US204169
申请日：1998-12-03
申请人： Hiroyuki Kishita , Masahiko Osada , Hiroaki Himi
发明人： Hiroyuki Kishita , Masahiko Osada , Hiroaki Himi
IPC分类号： G09G3/30 , G09G3/10
CPC分类号： G09G3/30 , G09G2310/0267 , G09G2310/0275 , G09G2330/023
摘要： A scan driver IC for an EL element in an EL display device supplies, in a positive field, a positive polarity scan voltage and an offset voltage which is higher than ground to scan side driver ICs from voltage supply circuits, and the scan side driver ICs set voltage of scan electrodes to be the offset voltage in the positive field, together with outputting the positive polarity scan voltage to the scan electrodes during electroluminescence timing. Consequently, a voltage of Vr-Vm is applied to the scan side driver ICs, and so the breakdown voltage can be lowered by an amount corresponding to the offset voltage Vm. Circuits for providing such voltages, for providing alternating current drive voltages, and for reducing power consumption of the drive circuits are also disclosed.
摘要翻译：用于EL显示装置中的EL元件的扫描驱动器IC在正场中提供正极性扫描电压和高于地的偏移电压以从电压供应电路扫描侧驱动器IC，并且扫描侧驱动器IC 将扫描电极的电压设定为正场中的偏移电压，同时在电致发光定时期间将正极性扫描电压输出到扫描电极。因此，向扫描侧驱动器IC施加Vr-Vm的电压，因此能够将击穿电压降低与偏移电压Vm对应的量。还公开了用于提供这种电压，用于提供交流驱动电压以及用于降低驱动电路的功耗的电路。

7. 发明申请

US20060231868A1 Semiconductor device for high voltage IC 审中-公开
标题翻译：高压IC半导体器件
公开(公告)号：US20060231868A1
公开(公告)日：2006-10-19
申请号：US11405399
申请日：2006-04-18
申请人： Akira Yamada , Hiroaki Himi , Nozomu Akagi , Junichi Nagata
发明人： Akira Yamada , Hiroaki Himi , Nozomu Akagi , Junichi Nagata
IPC分类号： H01L29/768
CPC分类号： H01L27/1203 , H03K17/102
摘要： A semiconductor device includes: a plurality of transistors connected in series between a ground potential and a predetermined potential; an input terminal provided by a gate terminal of the first step transistor; a plurality of resistors connected in series between the ground potential and the predetermined potential; and an output terminal provided by a predetermined potential side terminal of the Nth step transistor. A gate terminal of each transistor other than the first step transistor is sequentially connected between neighboring two resistors. One of the resistors defined as an Ith step resistor has a resistance, which is smaller than a resistance of a (I+1)th step resistor.
摘要翻译：一种半导体器件包括：串联连接在地电位和预定电位之间的多个晶体管; 由第一级晶体管的栅极端子提供的输入端子; 串联连接在地电位和预定电位之间的多个电阻器; 以及由第N级晶体管的预定电位侧端子提供的输出端子。除了第一级晶体管之外的每个晶体管的栅极端子依次连接在相邻的两个电阻之间。被定义为第I级步进电阻器的电阻器之一具有小于第（I + 1）级步进电阻器的电阻的电阻。

8. 发明授权

US5874768A Semiconductor device having a high breakdown voltage 失效
标题翻译：具有高击穿电压的半导体器件
公开(公告)号：US5874768A
公开(公告)日：1999-02-23
申请号：US965775
申请日：1997-11-07
申请人： Hitoshi Yamaguchi , Hiroaki Himi , Seiji Fujino
发明人： Hitoshi Yamaguchi , Hiroaki Himi , Seiji Fujino
IPC分类号： H01L21/336 , H01L27/12 , H01L29/78 , H01L29/36
CPC分类号： H01L29/7824 , H01L27/1203 , H01L29/66772
摘要： A high breakdown voltage semiconductor device formed in an SOI structure is disclosed. An MOS transistor composed of a drift layer, p well, a source, a gate, and a drain is formed in an island region surrounded by insulators on a semiconductor substrate. Furthermore, an electricfield-alleviating layer is formed in a bottom portion of the Si island region. The electric-field-alleviating layer is a semiconductor layer of exceeding low concentration, e.g., intrinsic, and therefore a virtual PIN structure is structured among the p well and the drift layer. Because the electric-field-alleviating layer corresponds to an I layer of the PIN structure, a depletion layer is created within the electric-field-alleviating layer when high voltage is applied to the MOS transistor, the high voltage is distributed throughout this depletion layer, and high breakdown voltage can be obtained.
摘要翻译：公开了一种以SOI结构形成的高耐压电压半导体器件。在由半导体衬底上的绝缘体围绕的岛状区域中形成由漂移层，阱阱，源极，栅极和漏极构成的MOS晶体管。此外，在Si岛区域的底部形成电场缓和层。电场缓和层是超低浓度的半导体层，例如固有的，因此在p阱和漂移层之间构成虚拟PIN结构。由于电场减缓层对应于PIN结构的I层，当高电压施加到MOS晶体管时，在电场减缓层内产生耗尽层，高电压分布在整个耗尽层，可以得到高的击穿电压。

9. 发明授权

US5525824A Semiconductor device with isolation regions 失效
标题翻译：具有隔离区域的半导体器件
公开(公告)号：US5525824A
公开(公告)日：1996-06-11
申请号：US337832
申请日：1994-11-08
申请人： Hiroaki Himi , Harutsugu Fukumoto , Seiji Fujino
发明人： Hiroaki Himi , Harutsugu Fukumoto , Seiji Fujino
IPC分类号： H01L21/762 , H01L21/76 , H01L21/761 , H01L27/088 , H01L27/12 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L27/1203 , H01L27/088 , Y10S148/012
摘要： A multi-channel type intelligent power IC which solves the problems of parasitic transistor and increase in an area of isolation region, both of which are inherent problem in a pn junction isolation substrate. The power IC also enhances heat-radiation performance. An n type first semiconductor substrate and p type second semiconductor substrate are directly bonded, and a buried oxide film is formed in a portion of a bonding interface thereof. Subsequently, a plurality of isolation trenches are formed and the first semiconductor substrate is separated into an SOI isolation region and a pn isolation region. Logic elements are then formed in the SOI isolation region, and power elements are formed in the pn isolation region. In the case wherein two or more logic elements are hereby formed, the logic elements are isolated by isolation trenches. In the case wherein two or more power elements are formed, a parasitic current extracting portion is formed between mutual power elements.
摘要翻译：一种多通道型智能电力IC，其解决了寄生晶体管的问题，并增加了隔离区域的面积，这两者都是pn结隔离衬底的固有问题。电源IC还增强了散热性能。 n型第一半导体衬底和p型第二半导体衬底直接接合，并且在其接合界面的一部分中形成掩埋氧化膜。随后，形成多个隔离沟槽，并将第一半导体衬底分离为SOI隔离区域和pn隔离区域。然后在SOI隔离区域中形成逻辑元件，并且在pn隔离区域中形成功率元件。在其中形成两个或更多个逻辑元件的情况下，逻辑元件通过隔离沟槽隔离。在形成两个以上的功率元件的情况下，在互功率元件之间形成有寄生电流提取部。

10. 发明授权

US5451547A Method of manufacturing semiconductor substrate 失效
标题翻译：制造半导体衬底的方法
公开(公告)号：US5451547A
公开(公告)日：1995-09-19
申请号：US934040
申请日：1992-08-25
申请人： Hiroaki Himi , Masaki Matsui , Tosiaki Nisizawa , Seiji Fujino
发明人： Hiroaki Himi , Masaki Matsui , Tosiaki Nisizawa , Seiji Fujino
IPC分类号： H01L21/18 , H01L21/302
CPC分类号： H01L21/187 , Y10S148/012
摘要： Disclosed is a method of manufacturing a semiconductor substrate by bonding two silicon crystalline wafers, and particularly, to a method of manufacturing a semiconductor substrate capable of reduced electrical resistance at the bonding interface. In the disclosed method, the silicon wafers to be bonded have at least one surface mirror-polished. Then they are washed, thus forming a natural oxide film on the surface. Then they are soaked in a concentrated HF solution for enough time to remove the oxide film formed on the surface. After that, the silicon wafers are soaked in ultra pure water to replace the fluorine atoms terminated on the surface thereof by OH groups, followed by drying. The silicon wafers thus treated are closely contacted with each other in such a manner that the mirror-polished surfaces are opposed to each other. The silicon wafers are thus bonded to each other by the hydrogen bonding forces due to the OH groups, and then heat treated for reinforcing the bonding.
摘要翻译：公开了通过粘合两个硅晶片来制造半导体衬底的方法，特别是涉及一种能够在接合界面处降低电阻的半导体衬底的制造方法。在所公开的方法中，待结合的硅晶片具有经镜面抛光的至少一个表面。然后将其洗涤，从而在表面上形成天然氧化膜。然后将它们浸在浓缩的HF溶液中足够的时间以除去在表面上形成的氧化膜。之后，将硅晶片浸泡在超纯水中，用OH基代替其表面上终止的氟原子，然后干燥。如此处理的硅晶片彼此紧密接触，使得镜面抛光的表面彼此相对。因此硅晶片由于OH基团的氢键力而彼此结合，然后进行热处理以加强粘结。

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