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1. 发明申请

US20090180333A1 Semiconductor memory column decoder device and method 有权
标题翻译：半导体存储器列解码器装置及方法
公开(公告)号：US20090180333A1
公开(公告)日：2009-07-16
申请号：US12008417
申请日：2008-01-10
申请人： Shigekazu Yamada , Tomoharu Tanaka
发明人： Shigekazu Yamada , Tomoharu Tanaka
IPC分类号： G11C16/14
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26
摘要： Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. In one or more embodiments, the erase control unit applies voltages to the well to erase the memory cells in a manner that avoids breaking down p-n junctions formed by transistors fabricated in the well. In another embodiment, high voltage transistors are used to selectively isolate the bit lines from and couple the bit lines to a peripheral circuit in pairs so that each high voltage transistor is shared by two bit lines.
摘要翻译：半导体存储器件和方法包括在阱中制造的闪存单元阵列，同一列中的存储单元彼此串联连接并连接到相应的位线。存储器件还包括列解码器，数据寄存器缓冲器单元，行解码器，擦除控制单元和输入/输出缓冲器单元。在一个或多个实施例中，擦除控制单元以避免由在井中制造的晶体管形成的p-n结分解的方式向阱施加电压以擦除存储器单元。在另一个实施例中，高压晶体管用于选择性地将位线隔离并将位线成对地耦合到外围电路，使得每个高压晶体管由两个位线共享。

2. 发明授权

US08503249B2 Semiconductor memory column decoder device and method 有权
公开(公告)号：US08503249B2
公开(公告)日：2013-08-06
申请号：US13194813
申请日：2011-07-29
申请人： Shigekazu Yamada , Tomoharu Tanaka
发明人： Shigekazu Yamada , Tomoharu Tanaka
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26
摘要： Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. In one or more embodiments, the erase control unit applies voltages to the well to erase the memory cells in a manner that avoids breaking down p-n junctions formed by transistors fabricated in the well. In another embodiment, high voltage transistors are used to selectively isolate the bit lines from and couple the bit lines to a peripheral circuit in pairs so that each high voltage transistor is shared by two bit lines.

3. 发明申请

US20120092933A1 MEMORY ERASE METHODS AND DEVICES 有权
标题翻译：记忆删除方法和设备
公开(公告)号：US20120092933A1
公开(公告)日：2012-04-19
申请号：US13331185
申请日：2011-12-20
申请人： Shigekazu YAMADA , Tomoharu Tanaka
发明人： Shigekazu YAMADA , Tomoharu Tanaka
IPC分类号： G11C16/16 , G11C16/06
CPC分类号： G11C16/16 , G11C16/30
摘要： Memory devices and erase methods for memories are disclosed, such as those adapted to discharge an erase voltage from a memory block while protecting low voltage string select gate transistors by maintaining the string select gate transistors in a turned on state during discharge.
摘要翻译：公开了用于存储器的存储器件和擦除方法，例如适于从存储器块放电擦除电压的存储器件和擦除方法，同时通过在放电期间将串选择栅极晶体管保持在导通状态来保护低压串选择栅极晶体管。

4. 发明授权

US08089816B2 Memory erase methods and devices 有权
标题翻译：内存擦除方法和设备
公开(公告)号：US08089816B2
公开(公告)日：2012-01-03
申请号：US12477270
申请日：2009-06-03
申请人： Shigekazu Yamada , Tomoharu Tanaka
发明人： Shigekazu Yamada , Tomoharu Tanaka
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C16/30
摘要： Memory devices and erase methods for memories are disclosed, such as those adapted to discharge an erase voltage from a memory block while protecting low voltage string select gate transistors by maintaining the string select gate transistors in a turned on state during discharge.
摘要翻译：公开了用于存储器的存储器件和擦除方法，例如适于从存储器块放电擦除电压的存储器件和擦除方法，同时通过在放电期间将串选择栅极晶体管保持在导通状态来保护低压串选择栅极晶体管。

5. 发明授权

US08000151B2 Semiconductor memory column decoder device and method 有权
标题翻译：半导体存储器列解码器装置及方法
公开(公告)号：US08000151B2
公开(公告)日：2011-08-16
申请号：US12008417
申请日：2008-01-10
申请人： Shigekazu Yamada , Tomoharu Tanaka
发明人： Shigekazu Yamada , Tomoharu Tanaka
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26
摘要： Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. In one or more embodiments, the erase control unit applies voltages to the well to erase the memory cells in a manner that avoids breaking down p-n junctions formed by transistors fabricated in the well. In another embodiment, high voltage transistors are used to selectively isolate the bit lines from and couple the bit lines to a peripheral circuit in pairs so that each high voltage transistor is shared by two bit lines.
摘要翻译：半导体存储器件和方法包括在阱中制造的闪存单元阵列，同一列中的存储单元彼此串联连接并连接到相应的位线。存储器件还包括列解码器，数据寄存器缓冲器单元，行解码器，擦除控制单元和输入/输出缓冲器单元。在一个或多个实施例中，擦除控制单元以避免由在井中制造的晶体管形成的p-n结分解的方式向阱施加电压以擦除存储器单元。在另一个实施例中，高压晶体管用于选择性地将位线隔离并将位线成对地耦合到外围电路，使得每个高压晶体管由两个位线共享。

6. 发明申请

US20100309730A1 MEMORY ERASE METHODS AND DEVICES 有权
标题翻译：记忆删除方法和设备
公开(公告)号：US20100309730A1
公开(公告)日：2010-12-09
申请号：US12477270
申请日：2009-06-03
申请人： Shigekazu Yamada , Tomoharu Tanaka
发明人： Shigekazu Yamada , Tomoharu Tanaka
IPC分类号： G11C16/16 , G11C16/04 , G11C16/06
CPC分类号： G11C16/16 , G11C16/30
摘要： Memory devices and erase methods for memories are disclosed, such as those adapted to discharge an erase voltage from a memory block while protecting low voltage string select gate transistors by maintaining the string select gate transistors in a turned on state during discharge.
摘要翻译：公开了用于存储器的存储器件和擦除方法，例如适于从存储器块放电擦除电压的存储器件和擦除方法，同时通过在放电期间将串选择栅极晶体管保持在导通状态来保护低压串选择栅极晶体管。

7. 发明授权

US08462559B2 Memory erase methods and devices 有权
标题翻译：内存擦除方法和设备
公开(公告)号：US08462559B2
公开(公告)日：2013-06-11
申请号：US13331185
申请日：2011-12-20
申请人： Shigekazu Yamada , Tomoharu Tanaka
发明人： Shigekazu Yamada , Tomoharu Tanaka
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C16/30
摘要： Memory devices and erase methods for memories are disclosed, such as those adapted to discharge an erase voltage from a memory block while protecting low voltage string select gate transistors by maintaining the string select gate transistors in a turned on state during discharge.
摘要翻译：公开了用于存储器的存储器件和擦除方法，例如适于从存储器块放电擦除电压的存储器件和擦除方法，同时通过在放电期间将串选择栅极晶体管保持在导通状态来保护低压串选择栅极晶体管。

8. 发明申请

US20110286282A1 SEMICONDUCTOR MEMORY COLUMN DECODER DEVICE AND METHOD 有权
标题翻译：半导体存储器解码器装置和方法
公开(公告)号：US20110286282A1
公开(公告)日：2011-11-24
申请号：US13194813
申请日：2011-07-29
申请人： Shigekazu Yamada , Tomoharu Tanaka
发明人： Shigekazu Yamada , Tomoharu Tanaka
IPC分类号： G11C16/06
CPC分类号： G11C16/14 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/26
摘要： Semiconductor memory devices and methods include a flash memory cell array fabricated in a well, with memory cells in the same column connected to each other in series and connected to a respective bit line. The memory devices also include a column decoder, a data register buffer unit, a row decoder, an erase control unit, and an input/output buffer unit. In one or more embodiments, the erase control unit applies voltages to the well to erase the memory cells in a manner that avoids breaking down p-n junctions formed by transistors fabricated in the well. In another embodiment, high voltage transistors are used to selectively isolate the bit lines from and couple the bit lines to a peripheral circuit in pairs so that each high voltage transistor is shared by two bit lines.
摘要翻译：半导体存储器件和方法包括在阱中制造的闪存单元阵列，同一列中的存储单元彼此串联连接并连接到相应的位线。存储器件还包括列解码器，数据寄存器缓冲器单元，行解码器，擦除控制单元和输入/输出缓冲器单元。在一个或多个实施例中，擦除控制单元以避免由在井中制造的晶体管形成的p-n结分解的方式向阱施加电压以擦除存储器单元。在另一个实施例中，高压晶体管用于选择性地将位线隔离并将位线成对地耦合到外围电路，使得每个高压晶体管由两个位线共享。

9. 发明授权

US09042180B2 Charge pump redundancy in a memory 有权
标题翻译：存储器中的电荷泵冗余
公开(公告)号：US09042180B2
公开(公告)日：2015-05-26
申请号：US13995166
申请日：2012-03-25
申请人： Toru Tanzawa , Tomoharu Tanaka
发明人： Toru Tanzawa , Tomoharu Tanaka
IPC分类号： G11C16/30 , G11C5/14 , G11C29/00
CPC分类号： G06F1/32 , G11C5/145 , G11C16/30 , G11C29/702
摘要： An integrated circuit includes a circuit block to utilize a load current at a load voltage from a power input and two or more charge pump arrays. The outputs of the charge pump arrays are coupled to the power input of the circuit block. The integrated circuit includes one or more modifiable elements to disable one or more of the two or more charge pump arrays.
摘要翻译：集成电路包括电路块，以利用来自电源输入和两个或更多个电荷泵阵列的负载电压的负载电流。电荷泵阵列的输出耦合到电路块的功率输入。集成电路包括一个或多个可修改的元件以禁用两个或更多个电荷泵阵列中的一个或多个。

10. 发明授权

US08964474B2 Architecture for 3-D NAND memory 有权
标题翻译： 3-D NAND存储器架构
公开(公告)号：US08964474B2
公开(公告)日：2015-02-24
申请号：US13524872
申请日：2012-06-15
申请人： Midori Morooka , Tomoharu Tanaka
发明人： Midori Morooka , Tomoharu Tanaka
IPC分类号： G11C16/00
CPC分类号： G11C16/0483 , G11C16/06 , G11C16/3427 , G11C2213/71
摘要： Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.
摘要翻译：描述了包括存储器单元串的堆叠阵列及其操作方法的装置。装置包括减少几个常用部件的使用的结构，允许给定半导体区域的更大的器件密度和更小的器件尺寸。

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