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    • 3. 发明申请
    • MEMORY CELL WITH A VERTICAL TRANSISTOR AND FABRICATION METHOD THEREOF
    • 具有垂直晶体管的存储单元及其制造方法
    • US20070187752A1
    • 2007-08-16
    • US11692163
    • 2007-03-27
    • Shian-Jyh LinYu-Sheng Hsu
    • Shian-Jyh LinYu-Sheng Hsu
    • H01L29/94H01L21/336
    • H01L29/66181H01L27/10841H01L27/10867
    • A memory cell with a vertical transistor has a semiconductor silicon substrate with a deep trench, in which the deep trench has a first sidewall region and a second sidewall region. A first insulating layer is formed overlying the first sidewall region. A second insulating layer is formed overlying the second sidewall region, in which the thickness of the first insulating layer is larger than the thickness of the second insulating layer. A gate electrode layer is sandwiched between the first insulating layer and the second insulating layer. A buried strap out-diffusion region is formed in the substrate adjacent to the second sidewall region, in which the buried strap out-diffusion region is located near the lower portion of the second insulating layer.
    • 具有垂直晶体管的存储单元具有深沟槽的半导体硅衬底,其中深沟槽具有第一侧壁区域和第二侧壁区域。 第一绝缘层形成在第一侧壁区域的上方。 第二绝缘层形成为覆盖第二侧壁区域,其中第一绝缘层的厚度大于第二绝缘层的厚度。 栅电极层夹在第一绝缘层和第二绝缘层之间。 掩埋带外扩散区域形成在与第二侧壁区域相邻的衬底中,其中掩埋带外延扩散区域位于第二绝缘层的下部附近。