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1. 发明授权

US07161396B1 CMOS power on reset circuit 有权
标题翻译： CMOS上电复位电路
公开(公告)号：US07161396B1
公开(公告)日：2007-01-09
申请号：US10644156
申请日：2003-08-20
申请人： Shi-Dong Zhou , Gubo Huang
发明人： Shi-Dong Zhou , Gubo Huang
IPC分类号： H03L7/00
CPC分类号： H03K17/223
摘要： A power-on reset circuit for generating a reset signal for an associated IC device includes a pull-up resistor connected between a supply voltage and a tracking node, a pull-down transistor connected between the tracking node and ground potential, and a voltage divider circuit connected between the supply voltage and ground potential. The voltage divider circuit has a first ratioed voltage node coupled to the gate of the pull-down transistor. For some embodiments, the voltage divider circuit includes a first resistor connected between the voltage supply and the first ratioed voltage node, a second resistor connected between the first ratioed voltage node and a second ratioed voltage node, a third resistor connected between the second ratioed voltage node and ground potential, and a shunt transistor connected between the second ratioed voltage node and ground potential has a gate responsive to the reset signal.
摘要翻译：用于产生关联IC器件的复位信号的上电复位电路包括连接在电源电压和跟踪节点之间的上拉电阻，连接在跟踪节点和接地电位之间的下拉晶体管，以及分压器电路连接在电源电压和地电位之间。分压器电路具有耦合到下拉晶体管的栅极的第一比例电压节点。对于一些实施例，分压器电路包括连接在电压源和第一比较电压节点之间的第一电阻器，连接在第一比较电压节点和第二比值电压节点之间的第二电阻器，连接在第二比率电压节点连接在第二比较电压节点和地电位之间的并联晶体管具有响应于复位信号的栅极。

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