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1. 发明授权

US10699658B2 GOA drive circuit 有权
公开(公告)号：US10699658B2
公开(公告)日：2020-06-30
申请号：US15539738
申请日：2017-05-08
申请人： Shenzhen China Star Optoelectronics Technology Co., Ltd.
发明人： Xiaowen Lv , Congwei Liao
IPC分类号： G09G3/36
摘要： A GOA drive circuit includes a multiple stage of GOA drive units. A GOA drive unit includes a pre-pulldown unit which is configured to disconnect a discharge path of a first voltage signal via the pull-down sustaining unit before the first voltage signal jumps from a low electric potential to a high electric potential. In the GOA drive circuit, the voltage stability of the key nodes in a circuit and the reliability of the timing can be ensured; overall performance of the GOA drive circuit can be improved; and a service life of a display device can be prolonged.

2. 发明授权

US10211346B2 Liquid crystal display panel having an active layer comprising more than two film layers and method for manufacturing the same 有权
公开(公告)号：US10211346B2
公开(公告)日：2019-02-19
申请号：US15329323
申请日：2017-01-11
申请人： Shenzhen China Star Optoelectronics Technology Co., Ltd.
发明人： Xiaowen Lv
IPC分类号： H01L29/786 , G02F1/1333 , G02F1/1368 , H01L29/34 , H01L29/66 , H01L21/02 , H01L21/306
摘要： Disclosed is a liquid crystal display panel and a method for manufacturing the same. The panel includes a thin-film transistor. An active layer in communication with a source and a drain of the thin-film transistor is formed by more than two film layers. The active layer contacts with a passivation layer of the panel on a non-high-speed deposited film layer of the active layer.

3. 发明授权

US09947699B2 Manufacturing method of dual gate oxide semiconductor TFT substrate and substrate thereof 有权
公开(公告)号：US09947699B2
公开(公告)日：2018-04-17
申请号：US15650972
申请日：2017-07-16
申请人： Shenzhen China Star Optoelectronics Technology Co., Ltd.
发明人： Shimin Ge , Hejing Zhang , Chihyuan Tseng , Chihyu Su , Wenhui Li , Longqiang Shi , Xiaowen Lv
IPC分类号： H01L21/44 , H01L29/786 , H01L27/12 , H01L29/49 , H01L29/24 , H01L21/02 , H01L27/32
CPC分类号： H01L27/1288 , H01L21/02565 , H01L21/02631 , H01L27/1225 , H01L27/127 , H01L27/3262 , H01L29/24 , H01L29/4908 , H01L29/78648 , H01L29/7869
摘要： A method for manufacturing a dual gate oxide semiconductor TFT substrate utilizes a halftone mask to implement a photo process, which not only accomplishes patterning to an oxide semiconductor layer but also obtains an oxide conductor layer with ion doping. The method implements patterning to a bottom gate isolation layer and a top gate isolation layer at the same time with one photolithographic process. The method implements patterning to second and third metal layers at the same time to obtain a first source, a first drain, a second source, a second drain, a first top gate and a second top gate with one photolithographic process. The method implements patterning to a second flat layer, a passivation layer and a top gate isolation layer at the same time with one photolithographic process. The number of photolithographic processes involved is reduced to nine so as to simplify the manufacturing process.

4. 发明申请

US20170373097A1 THIN-FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF 审中-公开
公开(公告)号：US20170373097A1
公开(公告)日：2017-12-28
申请号：US15701454
申请日：2017-09-12
申请人： Shenzhen China Star Optoelectronics Technology Co. Ltd.
发明人： Xiaowen Lv
IPC分类号： H01L27/12 , H01L29/51 , H01L29/49 , H01L29/786 , H01L29/66
CPC分类号： H01L27/1255 , H01L27/1225 , H01L27/1259 , H01L29/4908 , H01L29/517 , H01L29/66969 , H01L29/7869 , H01L51/52 , H01L51/56
摘要： A method is provided for manufacturing a thin film transistor array substrate, which includes: a substrate on which a thin film transistor and a storage capacitor are formed on the substrate. The storage capacitor includes a first electrode plate formed on the substrate, a gate isolation layer or an etching stopper layer formed on the first electrode plate, and a second electrode plate formed on the gate isolation layer or the etching stopper layer. The etching stopper layer may be formed on the gate isolation layer, of which one is partially etched and removed such that there is only one of the gate isolation layer and the etching stopper layer existing between the two electrode plates of the storage capacitor so as to reduce the overall thickness of the isolation layer of the storage capacitor. Thus, the capacitor occupies a smaller area and a higher aperture ratio may be achieved.

5. 发明授权

US09768202B2 TFT backplate structure comprising transistors having gate isolation layers of different thicknesses and manufacture method thereof 有权
公开(公告)号：US09768202B2
公开(公告)日：2017-09-19
申请号：US14426155
申请日：2014-09-19
申请人： Shenzhen China Star Optoelectronics Technology Co., Ltd.
发明人： Xiaowen Lv , Chihyuan Tseng , Chihyu Su , Hejing Zhang
IPC分类号： H01L27/12 , H01L29/78 , H01L21/16 , H01L21/00 , H01L29/24 , H01L21/47 , H01L29/786 , H01L21/77
CPC分类号： H01L27/1251 , H01L21/77 , H01L27/12 , H01L27/1225 , H01L27/1237 , H01L27/1288 , H01L29/7869
摘要： The present invention provides a TFT backplate structure and a manufacture method thereof. The TFT backplate structure comprises a switch TFT (T1) and a drive TFT (T2). The switch TFT (T1) is constructed by a first source/a first drain (61), a first gate (21), and a first etching stopper layer (51), a first oxide semiconductor layer (41), a first gate isolation layer (31) sandwiched in between. The drive TFT (T2) is constructed by a second source/a second drain (62), a second gate (22), and a second oxide semiconductor layer (42), a first etching stopper layer (51), a second gate isolation layer (32) sandwiched in between. The electrical properties of the switch TFT (T1) and the drive TFT (T2) are different. The switch TFT has smaller subthreshold swing to achieve fast charge and discharge, and the drive TFT has relatively larger subthreshold swing for controlling the current and the grey scale more precisely.

6. 发明授权

US09741858B2 Amorphous silicon semiconductor TFT backboard structure 有权
公开(公告)号：US09741858B2
公开(公告)日：2017-08-22
申请号：US14787772
申请日：2015-10-13
申请人： Shenzhen China Star Optoelectronics Technology Co., Ltd.
发明人： Xiaowen Lv , Chihyu Su , Yanhong Meng , Wenlin Mei
IPC分类号： H01L29/786
CPC分类号： H01L29/78627 , H01L29/78609 , H01L29/78621 , H01L29/78669
摘要： The present invention provides an amorphous silicon semiconductor TFT backboard structure, which includes a semiconductor layer (4) that has a multi-layer structure including a bottom amorphous silicon layer (41) in contact with a gate insulation layer (3), an N-type heavily-doped amorphous silicon layer (42) in contact with a source electrode (6) and a drain electrode (7), at least two N-type lightly-doped amorphous silicon layers (43) sandwiched between the bottom amorphous silicon layer (41) and the N-type heavily-doped amorphous silicon layer (42), a first intermediate amorphous silicon layer (44) separating every two adjacent ones of the lightly-doped amorphous silicon layers (43), and a second intermediate amorphous silicon layer (45) separating the N-type heavily-doped amorphous silicon layer (42) from the one of the lightly-doped amorphous silicon layers (43) that is closest to the N-type heavily-doped amorphous silicon layer (42). Such a structure further reduces the energy barrier between the drain electrode and the semiconductor layer, making injection of electron easier and ensuring the ON-state current is not lowered down and also helping increase the barrier for transmission of holes, lowering down the leakage current and improving reliability and electrical stability of the TFT.

7. 发明申请

US20170162707A1 AMORPHOUS SILICON SEMICONDUCTOR TFT BACKBOARD STRUCTURE 有权
公开(公告)号：US20170162707A1
公开(公告)日：2017-06-08
申请号：US14787772
申请日：2015-10-13
申请人： Shenzhen China Star Optoelectronics Technology Co., Ltd.
发明人： Xiaowen Lv , Chihyu Su , Yanhong Meng , Wenlin Mei
IPC分类号： H01L29/786
CPC分类号： H01L29/78627 , H01L29/78609 , H01L29/78621 , H01L29/78669
摘要： The present invention provides an amorphous silicon semiconductor TFT backboard structure, which includes a semiconductor layer (4) that has a multi-layer structure including a bottom amorphous silicon layer (41) in contact with a gate insulation layer (3), an N-type heavily-doped amorphous silicon layer (42) in contact with a source electrode (6) and a drain electrode (7), at least two N-type lightly-doped amorphous silicon layers (43) sandwiched between the bottom amorphous silicon layer (41) and the N-type heavily-doped amorphous silicon layer (42), a first intermediate amorphous silicon layer (44) separating every two adjacent ones of the lightly-doped amorphous silicon layers (43), and a second intermediate amorphous silicon layer (45) separating the N-type heavily-doped amorphous silicon layer (42) from the one of the lightly-doped amorphous silicon layers (43) that is closest to the N-type heavily-doped amorphous silicon layer (42). Such a structure further reduces the energy barrier between the drain electrode and the semiconductor layer, making injection of electron easier and ensuring the ON-state current is not lowered down and also helping increase the barrier for transmission of holes, lowering down the leakage current and improving reliability and electrical stability of the TFT.

8. 发明授权

US09553198B1 TFT substrate structure and manufacturing method thereof 有权
标题翻译： TFT基板结构及其制造方法
公开(公告)号：US09553198B1
公开(公告)日：2017-01-24
申请号：US14778087
申请日：2015-07-27
申请人： Shenzhen China Star Optoelectronics Technology Co., Ltd.
发明人： Xiaowen Lv
IPC分类号： H01L29/786 , H01L29/66 , H01L29/49 , H01L29/45
CPC分类号： H01L29/78669 , H01L29/4908 , H01L29/66765 , H01L29/78621
摘要： The present invention provides a TFT substrate structure and a manufacturing method thereof. The TFT substrate structure of the present invention includes an N-type lightly-doped amorphous silicon layer and an N-type heavily-doped amorphous silicon layer arranged between an amorphous silicon layer and a metal layer to form a gradient of doping concentration so as to reduce the potential barrier between the metal layer and the amorphous silicon layer, making injection of electrons easy and reducing the leakage current without lowering an operation current, thereby improving the electrical property of the TFT. The manufacturing method of a TFT substrate structure of the present invention includes forming an N-type lightly-doped amorphous silicon layer and an N-type heavily-doped amorphous silicon layer between an amorphous silicon layer and a metal layer to effectively reduce the potential barrier between the metal layer and the amorphous silicon layer, making injection of electrons easy and reducing the leakage current without lowering an operation current, thereby improving the electrical property of the TFT.
摘要翻译：本发明提供一种TFT基板结构及其制造方法。本发明的TFT基板结构包括非晶硅层和金属层之间的N型轻掺杂非晶硅层和N型重掺杂非晶硅层，以形成掺杂浓度梯度，从而降低金属层与非晶硅层之间的势垒，使电子注入容易，降低漏电流而不降低工作电流，提高TFT的电性能。本发明的TFT基板结构的制造方法包括在非晶硅层与金属层之间形成N型轻掺杂非晶硅层和N型重掺杂非晶硅层，以有效地降低势垒在金属层和非晶硅层之间，使电子注入容易，并降低漏电流而不降低工作电流，从而提高TFT的电性能。

9. 发明申请

US20160351723A1 CO-PLANAR OXIDE SEMICONDUCTOR TFT SUBSTRATE STRUCTURE AND MANUFACTURE METHOD THEREOF 有权
标题翻译： CO-PLANAL OXIDE SEMICONDUCTOR TFT基板结构及其制造方法
公开(公告)号：US20160351723A1
公开(公告)日：2016-12-01
申请号：US14771204
申请日：2015-06-18
申请人： Shenzhen China Star Optoelectronics Technology Co. Ltd.
发明人： Xiaowen Lv , Chihyuan Tseng
IPC分类号： H01L29/786 , H01L29/66 , H01L29/417 , H01L27/12
CPC分类号： H01L29/78696 , H01L21/44 , H01L27/124 , H01L27/1248 , H01L29/41733 , H01L29/66969 , H01L29/78609 , H01L29/7869
摘要： The present invention provides a co-planar oxide semiconductor TFT substrate structure and a manufacture method thereof. In the co-planar oxide semiconductor TFT substrate structure, the active layer comprises a main body and a plurality of short channels connected to the main body, and the plurality of short channels are separated with the plurality of strip metal electrodes to make the active layer possess higher mobility and lower leak current. Thus, the performance of the TFT element can be improved. The present invention provides a manufacture method of a co-planar oxide semiconductor TFT substrate structure. With forming the plurality of strip metal electrodes between the source and the drain, which are separately positioned, as deposing the oxide semiconductor layer, the plurality of short channels can be formed between the source and the drain. The method is simple and does not require additional mask or process to obtain the active layer structure different from prior art. The manufactured actively layer possesses higher mobility and lower leak current. Thus, the performance of the TFT element can be improved.
摘要翻译：本发明提供一种共面氧化物半导体TFT基板结构及其制造方法。在共面氧化物半导体TFT基板结构中，有源层包括主体和连接到主体的多个短沟道，并且多个短沟道与多个带状金属电极分离，以使活性层具有较高的流动性和较低的泄漏电流。因此，可以提高TFT元件的性能。本发明提供一种共面氧化物半导体TFT基板结构的制造方法。通过在分离定位的源极和漏极之间形成多个带状金属电极，作为去除氧化物半导体层，可以在源极和漏极之间形成多个短沟道。该方法简单，并且不需要额外的掩模或工艺来获得与现有技术不同的有源层结构。制作的活性层具有较高的迁移率和较低的漏电流。因此，可以提高TFT元件的性能。

10. 发明申请

US20160315106A1 THIN FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURE METHOD THEREOF 有权
标题翻译：薄膜晶体管阵列基板及其制造方法
公开(公告)号：US20160315106A1
公开(公告)日：2016-10-27
申请号：US14763818
申请日：2015-05-21
申请人： Shenzhen China Star Optoelectronics Technology Co. Ltd.
发明人： Xiaowen Lv
IPC分类号： H01L27/12 , H01L21/02 , H01L29/49 , H01L29/66 , H01L29/786 , H01L29/51
CPC分类号： H01L27/1255 , H01L27/1225 , H01L27/1259 , H01L29/4908 , H01L29/517 , H01L29/66969 , H01L29/7869 , H01L51/52 , H01L51/56
摘要： The present invention provides a thin film transistor array substrate and a manufacture method thereof, comprising: a substrate (1) and a thin film transistor and a storage capacitor formed on the substrate (1); the storage capacitor comprises a first electrode plate (31) on the substrate (1), a gate isolation layer (31) or an etching stopper layer (5) on the first electrode plate (31), a second electrode plate (32) on the gate isolation layer (3) or the etching stopper layer (5); there is only one isolation layer, which is the gate isolation layer or the etching stopper layer, existing between the two electrode plates of the storage capacitor in the aforesaid thin film transistor array substrate, the isolation layer thickness of the storage capacitor is thinner, and relatively, the capacitor occupies a smaller area and possesses a higher aperture ratio.
摘要翻译：本发明提供一种薄膜晶体管阵列基板及其制造方法，包括：基板（1）和形成在基板（1）上的薄膜晶体管和存储电容器; 存储电容器包括在基板（1）上的第一电极板（31），在第一电极板（31）上的栅极隔离层（31）或蚀刻停止层（5），第二电极板栅极隔离层（3）或蚀刻阻挡层（5）; 上述薄膜晶体管阵列基板中的存储电容器的两个电极板之间仅存在一个隔离层，即栅极隔离层或蚀刻停止层，存储电容器的隔离层厚度较薄，相对地，电容器占用更小的面积并且具有更高的开口率。

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