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    • 1. 发明申请
    • Method and device for reducing voltage stress at bootstrap point in electronic circuits
    • 用于降低电子电路自举点电压应力的方法和装置
    • US20090051639A1
    • 2009-02-26
    • US11894752
    • 2007-08-20
    • Sheng-Chao LiuChen-Ming ChenMing-Tien Lin
    • Sheng-Chao LiuChen-Ming ChenMing-Tien Lin
    • G09G3/36G11C19/00
    • G11C19/28G09G3/3677G09G2310/0286G09G2330/04
    • A discharging device is used to reduce the voltage level at a bootstrap point in an electronic circuit such as a shift register circuit. In such a circuit, a first transistor in a conducting state receives an input pulse and conveys it to the gate terminal of a second transistor, causing the second transistor to be in a conducting state. This gate terminal is known as a bootstrap point. After receiving the input pulse, an output pulse is produced at one drain/source terminal of the second transistor. During the time period of the output pulse, the first transistor is in a non-conducting state and the voltage level at the bootstrap point is high, imposing a stress upon the first transistor. A discharging circuit consisting of at least one transistor is coupled to the bootstrap point in order to reduce the voltage level at the output pulse period.
    • 放电装置用于降低诸如移位寄存器电路的电子电路中的自举点处的电压电平。 在这种电路中,导通状态的第一晶体管接收输入脉冲并将其传送到第二晶体管的栅极端子,使第二晶体管处于导通状态。 该门终端被称为引导点。 在接收到输入脉冲之后,在第二晶体管的一个漏极/源极端产生输出脉冲。 在输出脉冲的时间周期期间,第一晶体管处于非导通状态,并且自举点处的电压电平高,对第一晶体管施加应力。 由至少一个晶体管组成的放电电路耦合到自举点,以便降低输出脉冲周期的电压电平。
    • 2. 发明授权
    • Method and device for reducing voltage stress at bootstrap point in electronic circuits
    • 用于降低电子电路自举点电压应力的方法和装置
    • US08248353B2
    • 2012-08-21
    • US11894752
    • 2007-08-20
    • Sheng-Chao LiuChen-Ming ChenMing-Tien Lin
    • Sheng-Chao LiuChen-Ming ChenMing-Tien Lin
    • G09G3/36
    • G11C19/28G09G3/3677G09G2310/0286G09G2330/04
    • A discharging device is used to reduce the voltage level at a bootstrap point in an electronic circuit such as a shift register circuit. In such a circuit, a first transistor in a conducting state receives an input pulse and conveys it to the gate terminal of a second transistor, causing the second transistor to be in a conducting state. This gate terminal is known as a bootstrap point. After receiving the input pulse, an output pulse is produced at one drain/source terminal of the second transistor. During the time period of the output pulse, the first transistor is in a non-conducting state and the voltage level at the bootstrap point is high, imposing a stress upon the first transistor. A discharging circuit consisting of at least one transistor is coupled to the bootstrap point in order to reduce the voltage level at the output pulse period.
    • 放电装置用于降低诸如移位寄存器电路的电子电路中的自举点处的电压电平。 在这种电路中,导通状态的第一晶体管接收输入脉冲并将其传送到第二晶体管的栅极端子,使第二晶体管处于导通状态。 该门终端被称为引导点。 在接收到输入脉冲之后,在第二晶体管的一个漏极/源极端产生输出脉冲。 在输出脉冲的时间周期期间,第一晶体管处于非导通状态,并且自举点处的电压电平高,对第一晶体管施加应力。 由至少一个晶体管组成的放电电路耦合到自举点,以便降低输出脉冲周期的电压电平。
    • 5. 发明授权
    • Pixel array and display panel
    • 像素阵列和显示面板
    • US09007541B2
    • 2015-04-14
    • US13615598
    • 2012-09-14
    • Szu-Chieh ChenYu-Hsin TingChen-Ming ChenI-Fang ChenYi-Xuan HungDa-Wei Fan
    • Szu-Chieh ChenYu-Hsin TingChen-Ming ChenI-Fang ChenYi-Xuan HungDa-Wei Fan
    • G02F1/1362
    • H01L27/124G02F1/1362G02F1/136213G02F1/13624G02F1/136286H01L27/1255
    • A pixel array and a display panel are provided. The pixel array includes a plurality of pixel units. Each of the pixel units includes a first scan line, a second scan line, a data line, a first thin-film transistor, a second thin-film transistor, a first pixel electrode and a second pixel electrode. The first thin-film transistor is electrically connected to the first scan line and the data line. The first pixel electrode is electrically connected to the first thin-film transistor. The second thin-film transistor is electrically connected to the second scan line and the data line. The second pixel electrode is electrically connected to the second thin-film transistor. The orthogonal projection pattern of the first thin-film transistor on XY plane and the orthogonal projection pattern of the second thin-film transistor on XY plane are substantially the same.
    • 提供像素阵列和显示面板。 像素阵列包括多个像素单元。 每个像素单元包括第一扫描线,第二扫描线,数据线,第一薄膜晶体管,第二薄膜晶体管,第一像素电极和第二像素电极。 第一薄膜晶体管电连接到第一扫描线和数据线。 第一像素电极电连接到第一薄膜晶体管。 第二薄膜晶体管电连接到第二扫描线和数据线。 第二像素电极电连接到第二薄膜晶体管。 XY平面上的第一薄膜晶体管的正交投影图案和XY平面上的第二薄膜晶体管的正交投影图案基本相同。
    • 7. 发明申请
    • DISPLAY PANEL
    • 显示面板
    • US20130127801A1
    • 2013-05-23
    • US13610900
    • 2012-09-12
    • Yi-Xuan HungYu-Hsin TingChen-Ming ChenSzu-Chieh ChenDa-Wei FanChung-Lin Fu
    • Yi-Xuan HungYu-Hsin TingChen-Ming ChenSzu-Chieh ChenDa-Wei FanChung-Lin Fu
    • G06F3/038
    • G09G3/20G09G2310/0218G09G2310/0275G09G2310/0281G09G2310/0297
    • A display panel includes a plurality of first driving switches installed at a first side of the display panel, a plurality of second switches installed at a second side of the display panel, a plurality of first data lines, a plurality of second data lines, a plurality of scan lines, and a plurality of pixels. Each of the first driving switches includes a first input end and a plurality of first output ends. Each of the second driving switches includes a second input end and a plurality of second output ends. The first data lines are electrically connected to the first output ends. The second data lines are electrically connected to the second output ends. The plurality of pixels are electrically connected to the plurality of first data lines, second data lines and scan lines for displaying images. The first data lines and the second data lines are arranged interlacedly.
    • 显示面板包括安装在显示面板的第一侧的多个第一驱动开关,安装在显示面板的第二侧的多个第二开关,多个第一数据线,多个第二数据线, 多个扫描线,以及多个像素。 每个第一驱动开关包括第一输入端和多个第一输出端。 每个第二驱动开关包括第二输入端和多个第二输出端。 第一数据线电连接到第一输出端。 第二数据线电连接到第二输出端。 多个像素电连接到多个第一数据线,第二数据线和用于显示图像的扫描线。 第一数据线和第二数据线被交错布置。