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    • 3. 发明申请
    • DRAINAGE PUMP DEVICE FOR WASHING MACHINE AND WASHING MACHINE THEREWITH
    • 用于洗衣机和洗衣机的排水泵装置
    • US20140255155A1
    • 2014-09-11
    • US14355294
    • 2011-12-28
    • Haishan LiangPeishi LvSheng XuHaitao Li
    • Haishan LiangPeishi LvSheng XuHaitao Li
    • F04D19/02
    • F04D19/02D06F39/085F04D29/167F04D29/426F04D29/669
    • A draining pump for a washing machine and the washing machine thereof are disclosed. The washing machine includes an inlet system, and a draining system containing the draining pump device. The draining pump has a draining motor, a pump shell, a spinning blade and a filter, wherein, an inlet nozzle and an outlet nozzle are also arranged on the pump shell, and the pump shell is internally arranged with a front pump chamber and a rear pump chamber which are communicated according to the water draining sequence; the spinning blade is arranged in the rear pump chamber and installed coaxially with a revolving shaft of the drain motor, the filter is arranged in the front pump chamber, and a pressure relief plate with pressure relief holes is arranged at one side of the outlet of the filter corresponding to the water spinning blade.
    • 公开了一种用于洗衣机的排水泵及其洗衣机。 洗衣机包括入口系统和包含排水泵装置的排水系统。 排水泵具有排水马达,泵壳,旋转叶片和过滤器,其中,入口喷嘴和出口喷嘴也布置在泵壳体上,泵壳体内部布置有前泵室和 后泵室根据排水顺序连通; 纺纱刀片布置在后泵室中,与排水马达的旋转轴同轴设置,过滤器布置在前泵室中,并且具有卸压孔的压力释放板布置在出口的一侧 过滤器对应于水纺纱刀片。
    • 6. 发明授权
    • Asymmetric double buffering of bitstream data in a multi-core processor
    • 多核处理器中比特流数据的不对称双缓冲
    • US08595448B2
    • 2013-11-26
    • US12177253
    • 2008-07-22
    • Kuan FengHuo Ding LiXing S H LiuRong YanYu YuanSheng Xu
    • Kuan FengHuo Ding LiXing S H LiuRong YanYu YuanSheng Xu
    • G06F12/08
    • H04N19/42H04N19/44H04N19/91
    • An information handling system includes a multi-core processor that processes variable-length code (VLC) bitstream data. The bitstream data includes multiple codewords for interpretation. The processor includes a general purpose unit (GPU) and a special purpose unit (SPU). The GPU includes GPU buffers and the SPU includes SPU buffers. After populating one GPU buffer with bitstream data, the processor populates another GPU buffer with subsequent bitstream data. The processor may populate the GPU buffers in alternating fashion. The processor populates one SPU buffer with bitstream data while parsing bitstream data in the other SPU buffer. The GPU of the processor populates the SPU buffers in alternating fashion. The size of the GPU buffers may be a multiple of the size of the SPU buffers. After the SPU buffers consume the bitstream data from one GPU buffer, the other GPU buffer transfers its bitstream data to the SPU buffers for parsing.
    • 信息处理系统包括处理可变长度码(VLC)比特流数据的多核处理器。 比特流数据包括用于解释的多个码字。 处理器包括通用单元(GPU)和专用单元(SPU)。 GPU包括GPU缓冲区,SPU包括SPU缓冲区。 在使用比特流数据填充一个GPU缓冲器之后,处理器用随后的比特流数据填充另一个GPU缓冲器。 处理器可以以交替方式填充GPU缓冲器。 处理器在分析其他SPU缓冲区中的比特流数据时,使用比特流数据填充一个SPU缓冲区。 处理器的GPU以交替的方式填充SPU缓冲区。 GPU缓冲器的大小可以是SPU缓冲器的大小的倍数。 在SPU缓冲器从一个GPU缓冲器消耗比特流数据之后,另一个GPU缓冲器将其比特流数据传送到SPU缓冲器用于解析。
    • 7. 发明授权
    • Picture processing via a shared decoded picture pool
    • 通过共享解码图片池进行图片处理
    • US08300704B2
    • 2012-10-30
    • US12177212
    • 2008-07-22
    • Yu YuanRong YanSheng XuXing LiuHuo Ding Li
    • Yu YuanRong YanSheng XuXing LiuHuo Ding Li
    • H04N7/12
    • H04N19/436H04N19/423H04N19/44
    • An information handling system (IHS) may include a processor with multiple compute elements that decode pictures from an encoded video bitstream. Each compute element may perform a different part or sequential stage of a picture decoding process to obtain decoded pictures. A memory includes a decoded picture buffer that associates with a first stage of the sequential stages. The memory may also include respective decoded picture buffer snapshots for sequential stages other than the first sequential stage. A last sequential stage provides fully decoded pictures to a decoded picture pool in memory. The decoded picture buffer and decoded picture buffer snapshots may store pointers to decoded pictures in the decoded picture pool that the sequential stages need to perform decoding of pictures. In this manner, the sequential stages may share decoded pictures that the decoded picture pool stores.
    • 信息处理系统(IHS)可以包括具有从编码视频位流解码图像的多个计算单元的处理器。 每个计算元件可以执行图像解码处理的不同部分或顺序级以获得解码的图像。 存储器包括与顺序级的第一级相关联的解码图像缓冲器。 存储器还可以包括除了第一顺序级之外的顺序级的相应的解码图像缓冲器快照。 最后一个顺序阶段将完全解码的图像提供给存储器中的解码图像池。 解码图像缓冲器和解码图像缓冲器快照可以存储指向解码图像池中的解码图像的指针,顺序级需要对图像进行解码。 以这种方式,顺序级可以共享解码图像池存储的解码图像。
    • 10. 发明申请
    • PICTURE PROCESSING VIA A SHARED DECODED PICTURE POOL
    • 通过共享的解码图像池进行图像处理
    • US20100020885A1
    • 2010-01-28
    • US12177212
    • 2008-07-22
    • Yu YuanRong YanSheng XuXing LiuHuo Ding Li
    • Yu YuanRong YanSheng XuXing LiuHuo Ding Li
    • H04N7/26
    • H04N19/436H04N19/423H04N19/44
    • An information handling system (IHS) may include a processor with multiple compute elements that decode pictures from an encoded video bitstream. Each compute element may perform a different part or sequential stage of a picture decoding process to obtain decoded pictures. A memory includes a decoded picture buffer that associates with a first stage of the sequential stages. The memory may also include respective decoded picture buffer snapshots for sequential stages other than the first sequential stage. A last sequential stage provides fully decoded pictures to a decoded picture pool in memory. The decoded picture buffer and decoded picture buffer snapshots may store pointers to decoded pictures in the decoded picture pool that the sequential stages need to perform decoding of pictures. In this manner, the sequential stages may share decoded pictures that the decoded picture pool stores.
    • 信息处理系统(IHS)可以包括具有从编码视频位流解码图像的多个计算单元的处理器。 每个计算元件可以执行图像解码处理的不同部分或顺序级以获得解码的图像。 存储器包括与顺序级的第一级相关联的解码图像缓冲器。 存储器还可以包括除了第一顺序级之外的顺序级的相应的解码图像缓冲器快照。 最后一个顺序阶段将完全解码的图像提供给存储器中的解码图像池。 解码图像缓冲器和解码图像缓冲器快照可以存储指向解码图像池中的解码图像的指针,顺序级需要对图像进行解码。 以这种方式,顺序级可以共享解码图像池存储的解码图像。