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1. 发明申请

US20070089082A1 FREEWAY ROUTING SYSTEM FOR A GATE ARRAY 审中-公开
标题翻译：一个门阵列的自由路由系统
公开(公告)号：US20070089082A1
公开(公告)日：2007-04-19
申请号：US11557717
申请日：2006-11-08
申请人： Tong Liu , Jung-Cheun Lien , Sheng Feng , Eddy Huang , Chung-Yuan Sun , Naihui Liao , Weidong Xiong
发明人： Tong Liu , Jung-Cheun Lien , Sheng Feng , Eddy Huang , Chung-Yuan Sun , Naihui Liao , Weidong Xiong
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： G06F17/5054 , G06F17/5077 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： A freeway routing system for connecting input and output ports of interface groups of tiles in a field programmable gate array. The freeway system has a first set of routing conductors configured to transfer signals between the input ports of interface groups in a first tile of the field programmable gate array and the output ports of interface groups of other tiles in the field programmable gate array. The first set conductors include vertical conductors that form intersections with horizontal conductors and programmable interconnect elements located at the intersections of the vertical conductors and horizontal conductors in a diagonal orientation to connect each of the horizontal conductors to one of the vertical conductors.
摘要翻译：高速公路路由系统，用于连接现场可编程门阵列中瓦片接口组的输入和输出端口。高速公路系统具有第一组路由导体，其被配置为在现场可编程门阵列的第一瓦片中的接口组的输入端口与现场可编程门阵列中的其它瓦片的接口组的输出端口之间传送信号。第一组导体包括垂直导体，其形成与水平导体和位于垂直导体和水平导体的交叉点处的对准取向的可编程互连元件的交点，以将每个水平导体连接到一个垂直导体。

2. 发明申请

US20070075742A1 TILEABLE FIELD-PROGRAMMABLE GATE ARRAY ARCHITECTURE 失效
标题翻译：可行的可编程门阵列架构
公开(公告)号：US20070075742A1
公开(公告)日：2007-04-05
申请号：US11561705
申请日：2006-11-20
申请人： Sheng Feng , Jung-Cheun Lien , Eddy Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
发明人： Sheng Feng , Jung-Cheun Lien , Eddy Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17744
摘要： An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.
摘要翻译：一种装置包括FPGA，其包括包括多个FG，第一，第二和第三组路由导体以及多个IG的第一FPGA瓦片。 FG被布置成行和列，其中每个FG被配置为接收三级和常规输入信号，执行逻辑操作并且生成规则的输出信号。第三组路由导体耦合到FG的第一组输出端口，并被配置为接收信号，在FPGA瓦片内路由信号，并向FG的第三组输入端口提供输入信号。 IG围绕FG，使得一个IG位于每行和每列的每一端。每个IG耦合到第三组路由导体并且被配置为将信号从第三组路由导体传送到第一FPGA片外部。

3. 发明申请

US20060114024A1 Tileable field-programmable gate array architecture 失效
标题翻译：可拼接现场可编程门阵列架构
公开(公告)号：US20060114024A1
公开(公告)日：2006-06-01
申请号：US11335396
申请日：2006-01-18
申请人： Sheng Feng , Jung-Cheun Lien , Eddy Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
发明人： Sheng Feng , Jung-Cheun Lien , Eddy Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17744
摘要： An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.
摘要翻译：一种装置包括FPGA，其包括包括多个FG，第一，第二和第三组路由导体以及多个IG的第一FPGA瓦片。 FG被布置成行和列，其中每个FG被配置为接收三级和常规输入信号，执行逻辑操作并且生成规则的输出信号。第三组路由导体耦合到FG的第一组输出端口，并被配置为接收信号，在FPGA瓦片内路由信号，并向FG的第三组输入端口提供输入信号。 IG围绕FG，使得一个IG位于每行和每列的每一端。每个IG耦合到第三组路由导体并且被配置为将信号从第三组路由导体传送到第一FPGA片外部。

4. 发明授权

US07137095B1 Freeway routing system for a gate array 失效
标题翻译：高速公路路由系统为门阵列
公开(公告)号：US07137095B1
公开(公告)日：2006-11-14
申请号：US10077189
申请日：2002-02-15
申请人： Tong Liu , Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Naihui Liao , Weidong Xiong
发明人： Tong Liu , Jung-Cheun Lien , Sheng Feng , Eddy C. Huang , Chung-Yuan Sun , Naihui Liao , Weidong Xiong
IPC分类号： G06F17/50 , H03K19/177
CPC分类号： G06F17/5054 , G06F17/5077 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： A freeway routing system that connects interface groups in said field programmable gate array. The freeway system has a first set of routing conductors configured to transfer signals to the input ports of at least one interface group in a first tile of the field programmable gate array and configured to transfer signals from the output ports of other tiles in the field programmable gate array. The first set of conductors include vertical conductors that form intersections horizontal conductors and programmable interconnect elements located at the intersections of the vertical conductors and horizontal conductors in a diagonal orientation to connect each of horizontal conductors to one of the vertical conductors.
摘要翻译：连接所述现场可编程门阵列中的接口组的高速路由系统。高速公路系统具有第一组路由导体，其被配置为将信号传送到现场可编程门阵列的第一瓦片中的至少一个接口组的输入端口，并且被配置为从现场可编程的其它瓦片的输出端口传送信号门阵列第一组导体包括垂直导体，其形成交叉点水平导体和位于垂直导体和水平导体的交叉点处的对准方向的可编程互连元件，以将每个水平导体连接到垂直导体之一。

5. 发明授权

US06700404B1 Tileable field-programmable gate array architecture 有权
标题翻译：可拼接现场可编程门阵列架构
公开(公告)号：US06700404B1
公开(公告)日：2004-03-02
申请号：US10066398
申请日：2002-01-30
申请人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
发明人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
IPC分类号： H03K19177
CPC分类号： G06F17/5054 , G06F17/5077 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside of the first FPGA tile.
摘要翻译：一种装置包括现场可编程门阵列（FPGA）。所述FPGA包括第一FPGA瓦片，并且所述第一FPGA瓦片除了第一组路由导体和第二组布线导体以及多个布线导体之外，还包括多个功能组（FG），第三组布线导体接口组（IG）。多个FG布置成行和列，其中每个FG被配置为接收三次输入信号以及常规输入信号，执行逻辑运算并产生常规输出信号。第三组路由导体被耦合到FG的第一组输出端口并且被配置为接收信号，在第一FPGA瓦片内路由信号，并且向FG的第三组输入端口提供输入信号。多个IG围绕多个FG，使得一个IG位于每行和每列的每一端。每个IG耦合到第三组路由导体并且被配置为将信号从第三组路由导体传送到第一FPGA片外部。

6. 发明申请

US20080238477A1 TILEABLE FIELD-PROGRAMMABLE GATE ARRAY ARCHITECTURE 审中-公开
标题翻译：可行的可编程门阵列架构
公开(公告)号：US20080238477A1
公开(公告)日：2008-10-02
申请号：US12036470
申请日：2008-02-25
申请人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
发明人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
IPC分类号： H03K19/177
CPC分类号： G06F17/5054 , G06F17/5077 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.
摘要翻译：一种装置包括FPGA，其包括包括多个FG，第一，第二和第三组路由导体以及多个IG的第一FPGA瓦片。 FG被布置成行和列，其中每个FG被配置为接收三级和常规输入信号，执行逻辑操作并且生成规则的输出信号。第三组路由导体耦合到FG的第一组输出端口，并被配置为接收信号，在FPGA瓦片内路由信号，并向FG的第三组输入端口提供输入信号。 IG围绕FG，使得一个IG位于每行和每列的每一端。每个IG耦合到第三组路由导体并且被配置为将信号从第三组路由导体传送到第一FPGA片外部。

7. 发明授权

US07015719B1 Tileable field-programmable gate array architecture 有权
公开(公告)号：US07015719B1
公开(公告)日：2006-03-21
申请号：US11056957
申请日：2005-02-11
申请人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
发明人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17744
摘要： An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.

8. 发明授权

US07342416B2 Tileable field-programmable gate array architecture 失效
标题翻译：可拼接现场可编程门阵列架构
公开(公告)号：US07342416B2
公开(公告)日：2008-03-11
申请号：US11561705
申请日：2006-11-20
申请人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
发明人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
IPC分类号： H03K19/0177
CPC分类号： H03K19/17736 , H03K19/17744
摘要： An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.
摘要翻译：一种装置包括FPGA，其包括包括多个FG，第一，第二和第三组路由导体以及多个IG的第一FPGA瓦片。 FG被布置成行和列，其中每个FG被配置为接收三级和常规输入信号，执行逻辑操作并且生成规则的输出信号。第三组路由导体耦合到FG的第一组输出端口，并被配置为接收信号，在FPGA瓦片内路由信号，并向FG的第三组输入端口提供输入信号。 IG围绕FG，使得一个IG位于每行和每列的每一端。每个IG耦合到第三组路由导体并且被配置为将信号从第三组路由导体传送到第一FPGA片外部。

9. 发明授权

US07157938B2 Tileable field-programmable gate array architecture 失效
标题翻译：可拼接现场可编程门阵列架构
公开(公告)号：US07157938B2
公开(公告)日：2007-01-02
申请号：US11335396
申请日：2006-01-18
申请人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
发明人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
IPC分类号： H03K19/177
CPC分类号： H03K19/17736 , H03K19/17744
摘要： An apparatus includes an FPGA, which includes a first FPGA tile including a plurality of FGs, a first, second, and third set of routing conductors, and a plurality of IGs. The FGs are arranged in rows and columns with each FG being configured to receive tertiary and regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the FPGA tile, and provide input signals to the third set of input ports of the FGs. The IGs surround the FGs such that one IG is positioned at each end of each row and column. Each IG is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside the first FPGA tile.
摘要翻译：一种装置包括FPGA，其包括包括多个FG，第一，第二和第三组路由导体以及多个IG的第一FPGA瓦片。 FG被布置成行和列，其中每个FG被配置为接收三级和常规输入信号，执行逻辑操作并且生成规则的输出信号。第三组路由导体耦合到FG的第一组输出端口，并被配置为接收信号，在FPGA瓦片内路由信号，并向FG的第三组输入端口提供输入信号。 IG围绕FG，使得一个IG位于每行和每列的每一端。每个IG耦合到第三组路由导体并且被配置为将信号从第三组路由导体传送到第一FPGA片外部。

10. 发明授权

US06888375B2 Tileable field-programmable gate array architecture 有权
标题翻译：可拼接现场可编程门阵列架构
公开(公告)号：US06888375B2
公开(公告)日：2005-05-03
申请号：US10429002
申请日：2003-04-30
申请人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
发明人： Sheng Feng , Jung-Cheun Lien , Eddy C. Huang , Chung-Yuan Sun , Tong Liu , Naihui Liao , Weidong Xiong
IPC分类号： H03K19/177
CPC分类号： G06F17/5054 , G06F17/5077 , H03K19/17732 , H03K19/17736 , H03K19/17796
摘要： An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors and a second set of routing conductors and a plurality of interface groups (IGs). The plurality of FGs are arranged in rows and columns with each of the FGs being configured to receive tertiary input signals as well as regular input signals, perform a logic operation, and generate regular output signals. The third set of routing conductors is coupled to the first set of output ports of the FGs and configured to receive signals, route signals within the first FPGA tile, and provide input signals to the third set of input ports of the FGs. The plurality of IGs surround the plurality of FGs such that one IG is positioned at each end of each row and column. Each of the IGs is coupled to the third set of routing conductors and configured to transfer signals from the third set of routing conductors to outside of the first FPGA tile.
摘要翻译：一种装置包括现场可编程门阵列（FPGA）。所述FPGA包括第一FPGA瓦片，并且所述第一FPGA瓦片除了第一组路由导体和第二组布线导体以及多个布线导体之外，还包括多个功能组（FG），第三组布线导体接口组（IG）。多个FG布置成行和列，其中每个FG被配置为接收三次输入信号以及常规输入信号，执行逻辑运算并产生常规输出信号。第三组路由导体被耦合到FG的第一组输出端口并且被配置为接收信号，在第一FPGA瓦片内路由信号，并且向FG的第三组输入端口提供输入信号。多个IG围绕多个FG，使得一个IG位于每行和每列的每一端。每个IG耦合到第三组路由导体并且被配置为将信号从第三组路由导体传送到第一FPGA片外部。

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