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1. 发明申请

US20090081842A1 PROCESS FOR ATOMIC LAYER DEPOSITION 有权
标题翻译：原子层沉积过程
公开(公告)号：US20090081842A1
公开(公告)日：2009-03-26
申请号：US11861491
申请日：2007-09-26
申请人： Shelby F. Nelson , David H. Levy , Lyn M. Irving , Peter J. Cowdery-Corvan , Diane C. Freeman , Carolyn R. Ellinger
发明人： Shelby F. Nelson , David H. Levy , Lyn M. Irving , Peter J. Cowdery-Corvan , Diane C. Freeman , Carolyn R. Ellinger
IPC分类号： H01L21/336
CPC分类号： H01L27/1259 , B33Y80/00 , C23C16/407 , C23C16/45551 , C23C16/45595 , C23C16/545 , H01L27/1214 , H01L27/1225
摘要： The present invention relates to a process of making thin film electronic components and devices, such as thin film transistors, environmental barrier layers, capacitors, insulators and bus lines, where most or all of the layers are made by an atmospheric atomic layer deposition process.
摘要翻译：本发明涉及薄膜电子元件和薄膜晶体管，环境屏障层，电容器，绝缘子和总线线路的制造方法，其中大部分或全部层通过大气原子层沉积工艺制成。

2. 发明授权

US07851380B2 Process for atomic layer deposition 有权
标题翻译：原子层沉积工艺
公开(公告)号：US07851380B2
公开(公告)日：2010-12-14
申请号：US11861491
申请日：2007-09-26
申请人： Shelby F. Nelson , David H. Levy , Lyn M. Irving , Peter J. Cowdery-Corvan , Diane C. Freeman , Carolyn R. Ellinger
发明人： Shelby F. Nelson , David H. Levy , Lyn M. Irving , Peter J. Cowdery-Corvan , Diane C. Freeman , Carolyn R. Ellinger
IPC分类号： H01L21/31
CPC分类号： H01L27/1259 , B33Y80/00 , C23C16/407 , C23C16/45551 , C23C16/45595 , C23C16/545 , H01L27/1214 , H01L27/1225
摘要： The present invention relates to a process of making thin film electronic components and devices, such as thin film transistors, environmental barrier layers, capacitors, insulators and bus lines, where most or all of the layers are made by an atmospheric atomic layer deposition process.
摘要翻译：本发明涉及薄膜电子元件和薄膜晶体管，环境屏障层，电容器，绝缘子和总线线路的制造方法，其中大部分或全部层通过大气原子层沉积工艺制成。

3. 发明授权

US08207063B2 Process for atomic layer deposition 有权
标题翻译：原子层沉积工艺
公开(公告)号：US08207063B2
公开(公告)日：2012-06-26
申请号：US11627525
申请日：2007-01-26
申请人： Peter J. Cowdery-Corvan , David H. Levy , Shelby F. Nelson , Diane C. Freeman , Thomas D. Pawlik
发明人： Peter J. Cowdery-Corvan , David H. Levy , Shelby F. Nelson , Diane C. Freeman , Thomas D. Pawlik
IPC分类号： H01L21/20
CPC分类号： C23C16/407 , B33Y80/00 , C23C16/45551 , C23C16/545
摘要： The present invention relates to a process of making a zinc-oxide-based thin film semiconductor, for use in a transistor, comprising thin film deposition onto a substrate comprising providing a plurality of gaseous materials comprising at least first, second, and third gaseous materials, wherein the first gaseous material is a zinc-containing volatile material and the second gaseous material is reactive therewith such that when one of the first or second gaseous materials are on the surface of the substrate the other of the first or second gaseous materials will react to deposit a layer of material on the substrate and wherein the third gaseous material is inert with respect to reacting with the first or second gaseous materials.
摘要翻译：本发明涉及一种制造用于晶体管的氧化锌基薄膜半导体的方法，其包括在衬底上的薄膜沉积，包括提供多种气态材料，其包括至少第一，第二和第三气态材料其中所述第一气态材料是含锌挥发性材料，并且所述第二气态材料与其反应，使得当所述第一或第二气态材料中的一种位于所述基材的表面上时，所述第一或第二气态材料中的另一种将反应以在衬底上沉积一层材料，并且其中第三气态材料相对于与第一或第二气态材料的反应是惰性的。

4. 发明申请

US20090081826A1 PROCESS FOR MAKING DOPED ZINC OXIDE 有权
标题翻译：制造掺杂氧化锌的方法
公开(公告)号：US20090081826A1
公开(公告)日：2009-03-26
申请号：US11861455
申请日：2007-09-26
申请人： Peter J. Cowdery-Corvan , David H. Levy , Thomas D. Pawlik , Diane C. Freeman , Shelby F. Nelson
发明人： Peter J. Cowdery-Corvan , David H. Levy , Thomas D. Pawlik , Diane C. Freeman , Shelby F. Nelson
IPC分类号： H01L21/36
CPC分类号： H01L21/02576 , B33Y80/00 , C23C16/407 , C23C16/45504 , C23C16/45544 , C23C16/45551 , C23C16/45574 , H01L21/02554 , H01L21/02565 , H01L21/0262
摘要： The present invention relates to a process of making a zinc-oxide-based thin film semiconductor, for use in a transistor, comprising thin film deposition onto a substrate comprising providing a plurality of gaseous materials comprising first, second, and third gaseous materials, wherein the first gaseous material is a zinc-containing volatile material and the second gaseous material is reactive therewith such that when one of the first or second gaseous materials are on the surface of the substrate the other of the first or second gaseous materials will react to deposit a layer of material on the substrate, wherein the third gaseous material is inert and wherein a volatile indium-containing compound is introduced into the first reactive gaseous material or a supplemental gaseous material.
摘要翻译：本发明涉及一种制造用于晶体管的氧化锌基薄膜半导体的方法，其包括在衬底上的薄膜沉积，包括提供多种包含第一，第二和第三气态材料的气态材料，其中第一气体材料是含锌挥发性材料，第二气态材料与其反应，使得当第一或第二气态材料之一位于基材表面上时，第一或第二气态材料中的另一种将反应沉积衬底上的一层材料，其中所述第三气态材料是惰性的，并且其中将挥发性含铟化合物引入到所述第一反应性气态材料或补充气态材料中。

5. 发明授权

US07972898B2 Process for making doped zinc oxide 有权
标题翻译：制造掺杂氧化锌的方法
公开(公告)号：US07972898B2
公开(公告)日：2011-07-05
申请号：US11861455
申请日：2007-09-26
申请人： Peter J. Cowdery-Corvan , David H. Levy , Thomas D. Pawlik , Diane C. Freeman , Shelby F. Nelson
发明人： Peter J. Cowdery-Corvan , David H. Levy , Thomas D. Pawlik , Diane C. Freeman , Shelby F. Nelson
IPC分类号： C22B19/00 , C03C17/245
CPC分类号： H01L21/02576 , B33Y80/00 , C23C16/407 , C23C16/45504 , C23C16/45544 , C23C16/45551 , C23C16/45574 , H01L21/02554 , H01L21/02565 , H01L21/0262
摘要： The present invention relates to a process of making a zinc-oxide-based thin film semiconductor, for use in a transistor, comprising thin film deposition onto a substrate comprising providing a plurality of gaseous materials comprising first, second, and third gaseous materials, wherein the first gaseous material is a zinc-containing volatile material and the second gaseous material is reactive therewith such that when one of the first or second gaseous materials are on the surface of the substrate the other of the first or second gaseous materials will react to deposit a layer of material on the substrate, wherein the third gaseous material is inert and wherein a volatile indium-containing compound is introduced into the first reactive gaseous material or a supplemental gaseous material.
摘要翻译：本发明涉及一种制造用于晶体管的氧化锌基薄膜半导体的方法，其包括在衬底上的薄膜沉积，包括提供多种包含第一，第二和第三气态材料的气态材料，其中第一气体材料是含锌挥发性材料，第二气态材料与其反应，使得当第一或第二气态材料之一位于基材表面上时，第一或第二气态材料中的另一种将反应沉积衬底上的一层材料，其中所述第三气态材料是惰性的，并且其中将挥发性含铟化合物引入到所述第一反应性气态材料或补充气态材料中。

6. 发明申请

US20080182358A1 PROCESS FOR ATOMIC LAYER DEPOSITION 有权
标题翻译：原子层沉积过程
公开(公告)号：US20080182358A1
公开(公告)日：2008-07-31
申请号：US11627525
申请日：2007-01-26
申请人： Peter J. Cowdery-Corvan , David H. Levy , Shelby F. Nelson , Diane C. Freeman , Thomas D. Pawlik
发明人： Peter J. Cowdery-Corvan , David H. Levy , Shelby F. Nelson , Diane C. Freeman , Thomas D. Pawlik
IPC分类号： H01L21/20
CPC分类号： C23C16/407 , B33Y80/00 , C23C16/45551 , C23C16/545
摘要： The present invention relates to a process of making a zinc-oxide-based thin film semiconductor, for use in a transistor, comprising thin film deposition onto a substrate comprising providing a plurality of gaseous materials comprising at least first, second, and third gaseous materials, wherein the first gaseous material is a zinc-containing volatile material and the second gaseous material is reactive therewith such that when one of the first or second gaseous materials are on the surface of the substrate the other of the first or second gaseous materials will react to deposit a layer of material on the substrate and wherein the third gaseous material is inert with respect to reacting with the first or second gaseous materials.
摘要翻译：本发明涉及一种制造用于晶体管的氧化锌基薄膜半导体的方法，其包括在衬底上的薄膜沉积，包括提供多种气态材料，其包括至少第一，第二和第三气态材料其中所述第一气态材料是含锌挥发性材料，并且所述第二气态材料与其反应，使得当所述第一或第二气态材料中的一种位于所述基材的表面上时，所述第一或第二气态材料中的另一种将反应以在衬底上沉积一层材料，并且其中第三气态材料相对于与第一或第二气态材料的反应是惰性的。

7. 发明申请

US20140065831A1 PATTERNED THIN FILM DIELECTRIC LAYER FORMATION 有权
标题翻译：图形薄膜电介质层
公开(公告)号：US20140065831A1
公开(公告)日：2014-03-06
申请号：US13600287
申请日：2012-08-31
申请人： Carolyn R. Ellinger , David H. Levy , Shelby F. Nelson
发明人： Carolyn R. Ellinger , David H. Levy , Shelby F. Nelson
IPC分类号： H01L21/308
CPC分类号： H01L31/1884 , H01L21/02178 , H01L21/022 , H01L21/0228 , H01L21/02301 , H01L21/02315 , H01L21/02565 , H01L21/02573 , H01L21/0262 , H01L21/32 , H01L29/42384 , H01L29/4908 , H01L31/0392 , H01L31/03926 , Y02E10/50
摘要： A method of producing an inorganic thin film dielectric material layer includes providing a substrate. A first inorganic thin film dielectric material layer is deposited on the substrate using an atomic layer deposition process. The first inorganic thin film dielectric material layer is treated after its deposition. A patterned deposition inhibiting material layer is provided on the substrate. A second inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the deposition inhibiting material layer is not present using an atomic layer deposition process.
摘要翻译：无机薄膜电介质材料层的制造方法包括提供基板。使用原子层沉积工艺在衬底上沉积第一无机薄膜电介质材料层。第一种无机薄膜介电材料层在沉积后进行处理。在衬底上设置有图案化的沉积抑制材料层。使用原子层沉积工艺，在不存在沉积抑制材料层的基板的区域上选择性地沉积第二无机薄膜电介质材料层。

8. 发明申请

US20140065830A1 PATTERNED THIN FILM DIELECTRIC STACK FORMATION 有权
标题翻译：图形薄膜电介质堆积形成
公开(公告)号：US20140065830A1
公开(公告)日：2014-03-06
申请号：US13600274
申请日：2012-08-31
申请人： Carolyn R. Ellinger , David H. Levy , Shelby F. Nelson
发明人： Carolyn R. Ellinger , David H. Levy , Shelby F. Nelson
IPC分类号： H01L21/311
CPC分类号： H01L21/02348 , C23C16/04 , C23C16/45525 , H01L21/02178 , H01L21/022 , H01L21/0228 , H01L21/02299 , H01L21/02334 , H01L21/0234 , H01L29/4908
摘要： A method of producing a patterned inorganic thin film dielectric stack includes providing a substrate. A first patterned deposition inhibiting material layer is provided on the substrate. A first inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the first deposition inhibiting material layer is not present using an atomic layer deposition process. The first deposition inhibiting and first inorganic thin film dielectric material layers are simultaneously treated after deposition of the first inorganic thin film dielectric material layer. A second patterned deposition inhibiting material layer is provided on the substrate. A second inorganic thin film dielectric material layer is selectively deposited on a region of the substrate where the second deposition inhibiting material layer is not present using an atomic layer deposition process. The first and second inorganic thin film dielectric material layers form a patterned inorganic thin film dielectric stack.
摘要翻译：制造图案化无机薄膜电介质叠层的方法包括提供基板。第一图案化沉积抑制材料层设置在基板上。使用原子层沉积工艺，在不存在第一沉积抑制材料层的基板的区域上选择性地沉积第一无机薄膜电介质材料层。在沉积第一无机薄膜电介质材料层之后，同时处理第一沉积抑制和第一无机薄膜电介质材料层。第二图案化的沉积抑制材料层设置在基板上。使用原子层沉积工艺，在不存在第二沉积抑制材料层的基板的区域上选择性地沉积第二无机薄膜电介质材料层。第一和第二无机薄膜电介质材料层形成图案化的无机薄膜电介质叠层。

9. 发明申请

US20140061649A1 HIGH PERFORMANCE THIN FILM TRANSISTOR 有权
标题翻译：高性能薄膜晶体管
公开(公告)号：US20140061649A1
公开(公告)日：2014-03-06
申请号：US13600323
申请日：2012-08-31
申请人： Shelby F. Nelson , Carolyn R. Ellinger , David H. Levy
发明人： Shelby F. Nelson , Carolyn R. Ellinger , David H. Levy
IPC分类号： H01L29/786
CPC分类号： H01L29/4908 , H01L29/66969 , H01L29/7869
摘要： A transistor includes a substrate; a gate including a first electrically conductive layer stack on the substrate; and a first inorganic thin film dielectric layer on the substrate with the first inorganic thin film dielectric layer having a first pattern. A second inorganic thin film dielectric layer, having a second pattern, is in contact with the first inorganic thin film dielectric layer. The first inorganic thin film dielectric layer and the second thin film dielectric layer have the same material composition. A third inorganic thin film dielectric layer has a third pattern. A semiconductor layer is in contact with and has the same pattern as the third inorganic thin film dielectric material layer. A source/drain includes a second electrically conductive layer stack.
摘要翻译：晶体管包括衬底; 栅极，包括在所述衬底上的第一导电层堆叠; 以及第一无机薄膜电介质层，其具有第一图案的第一无机薄膜电介质层。具有第二图案的第二无机薄膜电介质层与第一无机薄膜电介质层接触。第一无机薄膜电介质层和第二薄膜电介质层具有相同的材料组成。第三无机薄膜电介质层具有第三图案。半导体层与第三无机薄膜电介质材料层接触并具有相同的图案。源极/漏极包括第二导电层堆叠。

10. 发明申请

US20140061648A1 THIN FILM TRANSISTOR INCLUDING DIELECTRIC STACK 审中-公开
标题翻译：薄膜晶体管，包括电介质堆叠
公开(公告)号：US20140061648A1
公开(公告)日：2014-03-06
申请号：US13600308
申请日：2012-08-31
申请人： David H. Levy , Carolyn R. Ellinger , Shelby F. Nelson
发明人： David H. Levy , Carolyn R. Ellinger , Shelby F. Nelson
IPC分类号： H01L29/786
CPC分类号： H01L29/4908
摘要： A transistor includes a substrate; a gate including a first electrically conductive layer stack on the substrate; and a first inorganic thin film dielectric layer on the substrate with the first inorganic thin film dielectric layer having a first pattern. A second inorganic thin film dielectric layer, having a second pattern, is in contact with the first inorganic thin film dielectric layer. The first inorganic thin film dielectric layer and the second thin film dielectric layer have the same material composition. A semiconductor layer has a third pattern. A source/drain includes a second electrically conductive layer stack.
摘要翻译：晶体管包括衬底; 栅极，包括在所述衬底上的第一导电层堆叠; 以及第一无机薄膜电介质层，其具有第一图案的第一无机薄膜电介质层。具有第二图案的第二无机薄膜电介质层与第一无机薄膜电介质层接触。第一无机薄膜电介质层和第二薄膜电介质层具有相同的材料组成。半导体层具有第三图案。源/漏包括第二导电层堆叠。

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