专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130332743A1 SPEED UP SECURE HASH ALGORITHM (SHA) USING SINGLE INSTRUCTION MULTIPLE DATA (SIMD) ARCHITECTURES 有权
标题翻译：使用单指令多重数据（SIMD）架构加速安全哈希算法（SHA）
公开(公告)号：US20130332743A1
公开(公告)日：2013-12-12
申请号：US13491207
申请日：2012-06-07
申请人： Shay GUERON , Vlad KRASNOV
发明人： Shay GUERON , Vlad KRASNOV
IPC分类号： G06F21/00 , H04L9/28
CPC分类号： G09C1/00 , G06F9/30007 , G06F9/30036 , G06F9/3895 , H04L9/0643 , H04L2209/125
摘要： A processing apparatus comprises logic to, according to a selected secure hash algorithm (SHA) algorithm, generate hash values by preparing message schedules for a plurality of message blocks in parallel using single instruction multiple date (SIMD) instructions and performing compression in serial, and logic to generate a message digest conforming to the secure hash algorithm (SHA) algorithm.
摘要翻译：一种处理装置包括根据所选择的安全散列算法（SHA）算法，通过使用单指令多重日期（SIMD）指令并行执行串行的并行执行多个消息块的消息调度来生成散列值的逻辑，以及生成符合安全散列算法（SHA）算法的消息摘要的逻辑。

2. 发明申请

US20130332707A1 SPEED UP BIG-NUMBER MULTIPLICATION USING SINGLE INSTRUCTION MULTIPLE DATA (SIMD) ARCHITECTURES 审中-公开
标题翻译：使用单个指令多种数据（SIMD）架构加快大量数字化
公开(公告)号：US20130332707A1
公开(公告)日：2013-12-12
申请号：US13491141
申请日：2012-06-07
申请人： Shay GUERON , Vlad KRASNOV
发明人： Shay GUERON , Vlad KRASNOV
IPC分类号： G06F9/302
CPC分类号： G06F9/3001 , G06F7/5324 , G06F9/30036 , G06F9/3893
摘要： A processing apparatus may be configured to include logic to generate a first set of vectors based on a first integer and a second set of vectors based on a second integer, logic to calculate sub products by multiplying the first set of vectors to the second set of vectors, logic to split each sub product into a first half and a second half and logic to generate a final result by adding together all first and second halves at respective digit positions.
摘要翻译：处理装置可以被配置为包括用于基于第一整数和第二组矢量生成基于第二整数的向量的第一集合的逻辑，用于通过将第一组矢量乘以第二组矢量来计算子乘积的逻辑矢量，将每个子产品分割成前半部分和后半部分的逻辑，以及通过将所有第一和第二半部分相加在各个数字位置来产生最终结果的逻辑。

3. 发明申请

US20130332742A1 SPEED UP SECURE HASH ALGORITHM (SHA) USING SINGLE INSTRUCTION MULTIPLE DATA (SIMD) ARCHITECTURES 有权
标题翻译：使用单指令多重数据（SIMD）架构加速安全哈希算法（SHA）
公开(公告)号：US20130332742A1
公开(公告)日：2013-12-12
申请号：US13490931
申请日：2012-06-07
申请人： Shay GUERON , Vlad KRASNOV
发明人： Shay GUERON , Vlad KRASNOV
IPC分类号： G06F21/00 , H04L9/28
CPC分类号： G09C1/00 , G06F9/30007 , G06F9/30036 , G06F9/3895 , H04L9/0643 , H04L2209/125
摘要： A processing apparatus may comprise logic to preprocess a message according to a selected secure hash algorithm (SHA) algorithm to generate a plurality of message blocks, logic to generate hash values by preparing message schedules in parallel using single instruction multiple data (SIMD) instructions for the plurality of message blocks and to perform compression in serial for the plurality of message blocks, and logic to generate a message digest conforming to the selected SHA algorithm.
摘要翻译：处理装置可以包括根据所选择的安全散列算法（SHA）算法来预处理消息以产生多个消息块的逻辑，用于通过使用单指令多数据（SIMD）指令并行准备消息调度来生成散列值的逻辑所述多个消息块并且为所述多个消息块串行地执行压缩，以及用于生成符合所选择的SHA算法的消息摘要的逻辑。

4. 发明申请

US20130301826A1 SYSTEM, METHOD, AND PROGRAM FOR PROTECTING CRYPTOGRAPHIC ALGORITHMS FROM SIDE-CHANNEL ATTACKS 审中-公开
标题翻译：用于保护来自边界通道攻击的克隆算法的系统，方法和程序
公开(公告)号：US20130301826A1
公开(公告)日：2013-11-14
申请号：US13466444
申请日：2012-05-08
申请人： Shay GUERON , Vlad KRASNOV
发明人： Shay GUERON , Vlad KRASNOV
IPC分类号： H04L9/28
CPC分类号： H04L9/002 , H04L2209/08
摘要： A system for protecting algorithms from side-channel attacks includes a digital processor having a first register, a second register, and a third register; an execution unit; and a processing unit. The execution unit executes an iterative loop for computing a value of a variable and sets a value of the first register based on either an operation or an instruction (or both) within the iterative loop. The processing unit stores the computed value of the variable in the second register and stores a predefined constant in the third register. Side-channel protection may also be provided by a method, a processor, and a program stored on a computer-readable medium.
摘要翻译：用于保护来自侧信道攻击的算法的系统包括具有第一寄存器，第二寄存器和第三寄存器的数字处理器; 一个执行单元; 和处理单元。执行单元执行用于计算变量的值的迭代循环，并且基于迭代循环内的操作或指令（或两者）来设置第一寄存器的值。处理单元将计算出的变量值存储在第二寄存器中，并将预定常量存储在第三寄存器中。侧通道保护也可以由存储在计算机可读介质上的方法，处理器和程序提供。

5. 发明申请

US20160056961A1 METHOD, APPARATUS, AND INSTRUCTIONS FOR SAFELY STORING SECRETS IN SYSTEM MEMORY 有权
标题翻译：方法，装置和说明书，用于在系统存储器中保存秘密
公开(公告)号：US20160056961A1
公开(公告)日：2016-02-25
申请号：US14467425
申请日：2014-08-25
申请人： Shay GUERON
发明人： Shay GUERON
IPC分类号： H04L9/32
CPC分类号： G06F12/1408 , G06F21/72 , G06F21/73 , G06F21/74 , G06F2212/1052 , G06F2221/2107 , H04L9/0637 , H04L9/0894 , H04L9/3226 , H04L63/083
摘要： Embodiments of an invention for method, apparatus, and instructions for safely storing secrets in system memory are disclosed. In one embodiment, a processor includes a hardware key, an instruction unit, and an encryption unit. The instruction unit is to receive an encryption instruction and a compare instruction. The encryption instruction is to have a first plaintext input value. The compare instruction is to have a second plaintext input value. The encryption unit is to, in response to the encryption instruction, encrypt the first plaintext input value using the hardware key to generate a ciphertext value, and, in response to the compare instruction, decrypt the ciphertext value using the hardware key to generate a plaintext output value and compare the plaintext output value to the second plaintext input value.
摘要翻译：公开了用于在系统存储器中安全地存储秘密的方法，装置和指令的发明的实施例。在一个实施例中，处理器包括硬件密钥，指令单元和加密单元。指令单元接收加密指令和比较指令。加密指令是具有第一个明文输入值。比较指令是具有第二个明文输入值。加密单元响应于加密指令，使用硬件密钥对第一明文输入值进行加密，以生成密文值，并且响应于比较指令，使用硬件密钥解密密文值以生成明文输出值，并将明文输出值与第二个明文输入值进行比较。

6. 发明申请

US20130188789A1 METHOD AND APPARATUS FOR GENERATING AN ADVANCED ENCRYPTION STANDARD (AES) KEY SCHEDULE 有权
公开(公告)号：US20130188789A1
公开(公告)日：2013-07-25
申请号：US13791224
申请日：2013-03-08
申请人： Shay GUERON , Martin DIXON , Srinivas CHENNUPATY , Mayank BOMB , Brent BOSWELL
发明人： Shay GUERON , Martin DIXON , Srinivas CHENNUPATY , Mayank BOMB , Brent BOSWELL
IPC分类号： H04L9/28
CPC分类号： H04L9/28 , G06F9/30007 , H04L9/0631 , H04L2209/125 , H04L2209/24
摘要： An Advanced Encryption Standard (AES) key generation assist instruction is provided. The AES key generation assist instruction assists in generating round keys used to perform AES encryption and decryption operations. The AES key generation instruction operates independent of the size of the cipher key and performs key generation operations in parallel on four 32-bit words thereby increasing the speed at which the round keys are generated. This instruction is easy to use in software. Hardware implementation of this instruction removes potential threats of software (cache access based) side channel attacks on this part of the AES algorithm.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式