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1. 发明授权

US07519750B2 Linear burst mode synchronizer for passive optical networks 有权
标题翻译：无源光网络的线性突发模式同步器
公开(公告)号：US07519750B2
公开(公告)日：2009-04-14
申请号：US11488124
申请日：2006-07-18
申请人： Shawn Scouten , Colin Cramm , Malcolm Stevens , Kenji Suzuki , Brian Wall , Med Belhadj
发明人： Shawn Scouten , Colin Cramm , Malcolm Stevens , Kenji Suzuki , Brian Wall , Med Belhadj
IPC分类号： G06F13/00 , G06F13/42 , G06F12/00 , H03L7/06 , H03K5/01
CPC分类号： H04L7/10 , H03L7/0807 , H03L7/087 , H04L7/033 , H04L2007/047
摘要： The present invention discloses a host receiver synchronizer for passive optical networks, and in particular a burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system having a non-data preamble of less than 250 ns, for recovering a clock signal from a subscriber data burst. The circuit comprises: an adjustable oscillator for generating an output clock signal in response to a signal at an input thereof; a first comparator for comparing a frequency and phase of the output clock signal to that of a reference signal and feeding back a first feedback signal to the oscillator input; and a second comparator for comparing the frequency and phase of the output clock signal to that of the data burst and feeding back a second feedback signal to the oscillator input once the output clock signal is locked in frequency with the reference signal. The output clock signal is locked in frequency and phase to the data burst before receipt of the last bit of the preamble. The present invention is advantageous in that the receiver circuit improves synchronized jitter performance over the prior art solutions so that additional timing margin is provided, thereby allowing longer fiber lengths to be supported.
摘要翻译：本发明公开了一种用于无源光网络的主机接收机同步器，特别是具有小于250ns的非数据前导码的突发异步通信系统中的主机接收机中的突发时钟数据恢复电路，用于从订户数据突发。该电路包括：可调节振荡器，用于响应于其输入端的信号产生输出时钟信号; 第一比较器，用于将输出时钟信号的频率和相位与参考信号的频率和相位进行比较，并将第一反馈信号反馈到振荡器输入; 以及第二比较器，用于在输出时钟信号与参考信号锁定频率时，将输出时钟信号的频率和相位与数据脉冲串的频率和相位进行比较，并将第二反馈信号反馈到振荡器输入。在接收到前同步码的最后一位之前，输出时钟信号被锁定在数据脉冲串的频率和相位上。本发明的优点在于接收机电路提高了现有技术解决方案的同步抖动性能，从而提供额外的时序余量，从而允许支持更长的光纤长度。

2. 发明申请

US20080022143A1 Linear burst mode synchronizer for passive optical networks 有权
标题翻译：无源光网络的线性突发模式同步器
公开(公告)号：US20080022143A1
公开(公告)日：2008-01-24
申请号：US11488124
申请日：2006-07-18
申请人： Shawn Scouten , Colin Cramm , Malcolm Stevens , Kenji Suzuki , Brian Wall , Med Belhadj
发明人： Shawn Scouten , Colin Cramm , Malcolm Stevens , Kenji Suzuki , Brian Wall , Med Belhadj
IPC分类号： G06F1/12
CPC分类号： H04L7/10 , H03L7/0807 , H03L7/087 , H04L7/033 , H04L2007/047
摘要： The present invention discloses a host receiver synchronizer for passive optical networks, and in particular a burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system having a non-data preamble of less than 250 ns, for recovering a clock signal from a subscriber data burst. The circuit comprises: an adjustable oscillator for generating an output clock signal in response to a signal at an input thereof; a first comparator for comparing a frequency and phase of the output clock signal to that of a reference signal and feeding back a first feedback signal to the oscillator input; and a second comparator for comparing the frequency and phase of the output clock signal to that of the data burst and feeding back a second feedback signal to the oscillator input once the output clock signal is locked in frequency with the reference signal. The output clock signal is locked in frequency and phase to the data burst before receipt of the last bit of the preamble. The present invention is advantageous in that the receiver circuit improves synchronized jitter performance over the prior art solutions so that additional timing margin is provided, thereby allowing longer fiber lengths to be supported.
摘要翻译：本发明公开了一种用于无源光网络的主机接收机同步器，特别是具有小于250ns的非数据前导码的突发异步通信系统中的主机接收机中的突发时钟数据恢复电路，用于从订户数据突发。该电路包括：可调节振荡器，用于响应于其输入端的信号产生输出时钟信号; 第一比较器，用于将输出时钟信号的频率和相位与参考信号的频率和相位进行比较，并将第一反馈信号反馈到振荡器输入; 以及第二比较器，用于在输出时钟信号与参考信号锁定频率时，将输出时钟信号的频率和相位与数据脉冲串的频率和相位进行比较，并将第二反馈信号反馈到振荡器输入。在接收到前同步码的最后一位之前，输出时钟信号被锁定在数据脉冲串的频率和相位上。本发明的优点在于接收机电路提高了现有技术解决方案的同步抖动性能，从而提供额外的时序余量，从而允许支持更长的光纤长度。

3. 发明申请

US20090016477A1 Signal timing phase selection and timing acquisition apparatus and techniques 有权
标题翻译：信号定时相位选择和定时采集装置及技术
公开(公告)号：US20090016477A1
公开(公告)日：2009-01-15
申请号：US11822725
申请日：2007-07-09
申请人： Colin Cramm , Shawn Scouten , Kenji Suzuki , Brian Wall , Malcolm Stevens
发明人： Colin Cramm , Shawn Scouten , Kenji Suzuki , Brian Wall , Malcolm Stevens
IPC分类号： H03D3/24
CPC分类号： H04L7/0337 , H03L7/0812 , H03L7/099
摘要： Signal timing phase selection and timing acquisition apparatus and techniques are disclosed. A timing phase that is most closely aligned with a phase of information carried by a received signal is selected from a plurality of timing phases. The selected timing phase may be used, for example, as a reference signal for a phase detector in a Phase-Locked Loop (PLL). The received signal may be sampled one or more times per timing phase. In a multiple-sample implementation, the samples may be used for timing phase selection, for detection of a known initial pattern of a burst of information to thereby detect the start time of a an information burst, or both.
摘要翻译：公开了信号定时相位选择和定时获取装置和技术。从多个定时阶段中选择与接收信号承载的信息的相位最接近的定时相位。所选择的定时相位可以用作例如锁相环（PLL）中的相位检测器的参考信号。每个定时相位可以对接收到的信号进行一次或多次采样。在多样本实现中，样本可以用于定时相位选择，用于检测信息突发的已知初始模式，从而检测信息突发的开始时间，或两者。

4. 发明授权

US07848474B2 Signal timing phase selection and timing acquisition apparatus and techniques 有权
标题翻译：信号定时相位选择和定时采集装置及技术
公开(公告)号：US07848474B2
公开(公告)日：2010-12-07
申请号：US11822725
申请日：2007-07-09
申请人： Colin Cramm , Shawn Scouten , Kenji Suzuki , Brian Wall , Malcolm Stevens
发明人： Colin Cramm , Shawn Scouten , Kenji Suzuki , Brian Wall , Malcolm Stevens
IPC分类号： H03D3/24
CPC分类号： H04L7/0337 , H03L7/0812 , H03L7/099
摘要： Signal timing phase selection and timing acquisition apparatus and techniques are disclosed. A timing phase that is most closely aligned with a phase of information carried by a received signal is selected from a plurality of timing phases. The selected timing phase may be used, for example, as a reference signal for a phase detector in a Phase-Locked Loop (PLL). The received signal may be sampled one or more times per timing phase. In a multiple-sample implementation, the samples may be used for timing phase selection, for detection of a known initial pattern of a burst of information to thereby detect the start time of a an information burst, or both.
摘要翻译：公开了信号定时相位选择和定时获取装置和技术。从多个定时阶段中选择与接收信号承载的信息的相位最接近的定时相位。所选择的定时相位可以用作例如锁相环（PLL）中的相位检测器的参考信号。每个定时相位可以对接收到的信号进行一次或多次采样。在多样本实现中，样本可以用于定时相位选择，用于检测信息突发的已知初始模式，从而检测信息突发的开始时间，或两者。

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