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1. 发明授权

US06651225B1 Dynamic evaluation logic system and method 失效
标题翻译：动态评估逻辑系统及方法
公开(公告)号：US06651225B1
公开(公告)日：2003-11-18
申请号：US09546554
申请日：2000-04-10
申请人： Sharon Sheau-Pyng Lin , Ping-Sheng Tseng , Chwen-Cher Chang , Su-Jen Hwang
发明人： Sharon Sheau-Pyng Lin , Ping-Sheng Tseng , Chwen-Cher Chang , Su-Jen Hwang
IPC分类号： G06F1750
CPC分类号： G06F17/5027 , G06F17/5022
摘要： In a verification system, a dynamic logic evaluation system and method dynamically calculates the minimum evaluation time for each input. Thus, this system and method will remove the performance burden that a fixed and statically calculated evaluation time would introduce. By dynamically calculating different evaluation times based on the input, 99% of the inputs will not be delayed for the sake of 1% of the inputs that actually need the worst possible evaluation time. The dynamic logic evaluation system and method comprises a global control unit coupled to a propagation detector, where the propagation detector is placed in each FPGA chip. The propagation detector in the FPGA chip alerts the global control unit of any input data that is currently propagating within the FPGA chips. A master clock controls the operation of this dynamic evaluation system and method. As long as any input data is propagating, the global control unit will prevent the next input from being provided to the FPGA chips for evaluation. Once the output has stabilized, the global control unit will then instruct the system to accept and process the next set of input data. Thus, the global control unit in conjunction with the propagation detectors can dynamically provide varying evaluation time periods based on the needs of the input data. Whether the system needs longer or shorter evaluation times, the system will dynamically adjust the amount of time necessary to properly process that input and then move on to the next evaluation time for the next set of inputs.
摘要翻译：在验证系统中，动态逻辑评估系统和方法动态地计算每个输入的最小评估时间。因此，该系统和方法将消除固定和静态计算的评估时间将引入的性能负担。通过根据输入动态计算不同的评估时间，为了实际需要最差可能的评估时间的1％的输入，99％的输入将不会被延迟。动态逻辑评估系统和方法包括耦合到传播检测器的全局控制单元，其中传播检测器被放置在每个FPGA芯片中。 FPGA芯片中的传播检测器向全局控制单元报告当前在FPGA芯片内传播的任何输入数据。主时钟控制这种动态评估系统和方法的运行。只要任何输入数据正在传播，全局控制单元将阻止将下一个输入提供给FPGA芯片进行评估。一旦输出稳定，全局控制单元将指示系统接受并处理下一组输入数据。因此，全局控制单元结合传播检测器可以基于输入数据的需要动态地提供变化的评估时间段。无论系统是否需要更长或更短的评估时间，系统将动态调整正确处理该输入所需的时间量，然后进入下一组输入的下一个评估时间。

2. 发明申请

US20060117274A1 Behavior processor system and method 审中-公开
标题翻译：行为处理器系统和方法
公开(公告)号：US20060117274A1
公开(公告)日：2006-06-01
申请号：US09918600
申请日：2001-07-30
申请人： Ping-Sheng Tseng , Yogesh Goel , Su-Jen Hwang , James Lee , Kun-Hsu Shen
发明人： Ping-Sheng Tseng , Yogesh Goel , Su-Jen Hwang , James Lee , Kun-Hsu Shen
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5027 , G06F2217/86
摘要： The debug system described in this patent specification provides a system that generates hardware elements from normally non-synthesizable code elements for placement on an FPGA device. This particular FPGA device is called a Behavior Processor. This Behavior Processor executes in hardware those code constructs that were previously executed in software. When some condition is satisfied (e.g., If . . . then . . . else loop) which requires some intervention by the workstation or the software model, the Behavior Processor works with an Xtrigger device to send a callback signal to the workstation for immediate response.
摘要翻译：本专利说明书中描述的调试系统提供了一种从通常不可合成的代码元件产生硬件元件的系统，用于放置在FPGA器件上。这个特定的FPGA器件被称为行为处理器。该行为处理器以硬件方式执行先前在软件中执行的代码结构。当需要工作站或软件模型进行干预的某些条件（例如，如果...然后... else循环）时，行为处理器与Xtrigger设备一起发送回呼信号到工作站以立即响应。

3. 发明申请

US20110041105A1 INTEGRATED DMA PROCESSOR AND PCI EXPRESS SWITCH FOR A HARDWARE-BASED FUNCTIONAL VERIFICATION SYSTEM 有权
标题翻译：集成DMA处理器和基于硬件的功能验证系统的PCI EXPRESS SWITCH
公开(公告)号：US20110041105A1
公开(公告)日：2011-02-17
申请号：US12541864
申请日：2009-08-14
申请人： Ching-Ping Chou , Su-Jen Hwang , Teng-I Yu
发明人： Ching-Ping Chou , Su-Jen Hwang , Teng-I Yu
IPC分类号： G06F17/50
CPC分类号： G06F13/28
摘要： A method and system for facilitating communication between a host system and one or more hardware-based functional verification systems. The one or more hardware-based functional verification systems verify the functionality of electronic circuit designs. A controller switch comprises a host interface connecting to a host system, and a plurality of device ports. Each device port connects to a hardware emulator. The controller switch further comprises a plurality of direct memory access (DMA) engines and a plurality of execution units. An execution unit comprises an instruction cache and memory storing at least one DMA instruction and at least one address for performing a software instruction and a plurality of execution unit registers.
摘要翻译：一种用于促进主机系统与一个或多个基于硬件的功能验证系统之间的通信的方法和系统。一个或多个基于硬件的功能验证系统验证电子电路设计的功能。控制器交换机包括连接到主机系统的主机接口和多个设备端口。每个设备端口连接到硬件仿真器。控制器开关还包括多个直接存储器访问（DMA）引擎和多个执行单元。执行单元包括存储至少一个DMA指令的指令高速缓存和存储器，以及用于执行软件指令的至少一个地址和多个执行单元寄存器。

4. 发明授权

US08327039B2 Integrated DMA processor and PCI express switch for a hardware-based functional verification system 有权
标题翻译：集成DMA处理器和PCI Express交换机，用于基于硬件的功能验证系统
公开(公告)号：US08327039B2
公开(公告)日：2012-12-04
申请号：US12541864
申请日：2009-08-14
申请人： Ching-Ping Chou , Su-Jen Hwang , Teng-I Yu
发明人： Ching-Ping Chou , Su-Jen Hwang , Teng-I Yu
IPC分类号： G06F13/28 , G06F3/00 , G06F5/00
CPC分类号： G06F13/28
摘要： A method and system for facilitating communication between a host system and one or more hardware-based functional verification systems. The one or more hardware-based functional verification systems verify the functionality of electronic circuit designs. A controller switch comprises a host interface connecting to a host system, and a plurality of device ports. Each device port connects to a hardware emulator. The controller switch further comprises a plurality of direct memory access (DMA) engines and a plurality of execution units. An execution unit comprises an instruction cache and memory storing at least one DMA instruction and at least one address for performing a software instruction and a plurality of execution unit registers.
摘要翻译：一种用于促进主机系统与一个或多个基于硬件的功能验证系统之间的通信的方法和系统。一个或多个基于硬件的功能验证系统验证电子电路设计的功能。控制器交换机包括连接到主机系统的主机接口和多个设备端口。每个设备端口连接到硬件仿真器。控制器开关还包括多个直接存储器访问（DMA）引擎和多个执行单元。执行单元包括存储至少一个DMA指令的指令高速缓存和存储器，以及用于执行软件指令的至少一个地址和多个执行单元寄存器。

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