专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120104510A1 CMOS PROCESS TO IMPROVE SRAM YIELD 有权
标题翻译： CMOS工艺改进SRAM输出
公开(公告)号：US20120104510A1
公开(公告)日：2012-05-03
申请号：US13284519
申请日：2011-10-28
申请人： Shaofeng Yu , Russell Carlton McMullan , Wah Kit Loh
发明人： Shaofeng Yu , Russell Carlton McMullan , Wah Kit Loh
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L27/1104 , H01L21/823814 , H01L21/823864 , H01L21/823871 , H01L27/0922 , H01L29/0847
摘要： An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact.
摘要翻译：包含SAR SRAM和CMOS逻辑的集成电路，其中SAR SRAM单元的栅极延伸上的侧壁间隔物比逻辑PMOS栅极上的侧壁间隔更薄，使得漏极节点SRAM PSD层的深度保持在伸展接触。形成包含SAR SRAM和CMOS逻辑的集成电路的过程，包括选择性地蚀刻在SAR SRAM单元的栅极延伸上的侧壁间隔物，使得漏极节点SRAM PSD层的深度保持在拉伸接触下。形成包含SAR SRAM和CMOS逻辑的集成电路的过程，包括在漏极节点SRAM PSD层中选择性地注入额外的p型掺杂剂，使得漏极节点SRAM PSD层的深度保持在拉伸接触下。

2. 发明授权

US08603875B2 CMOS process to improve SRAM yield 有权
公开(公告)号：US08603875B2
公开(公告)日：2013-12-10
申请号：US13284519
申请日：2011-10-28
申请人： Shaofeng Yu , Russell Carlton McMullan , Wah Kit Loh
发明人： Shaofeng Yu , Russell Carlton McMullan , Wah Kit Loh
IPC分类号： H01L21/8238
CPC分类号： H01L27/1104 , H01L21/823814 , H01L21/823864 , H01L21/823871 , H01L27/0922 , H01L29/0847
摘要： An integrated circuit containing an SAR SRAM and CMOS logic, in which sidewall spacers on the gate extension of the SAR SRAM cell are thinner than sidewall spacers on the logic PMOS gates, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively etch the sidewall spacers on the on the gate extension of the SAR SRAM cell, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact. A process of forming an integrated circuit containing an SAR SRAM and CMOS logic, including selectively implanting extra p-type dopants in the drain node SRAM PSD layer, so that the depth of the drain node SRAM PSD layer is maintained under the stretch contact.

3. 发明授权

US08467233B2 Asymmetric static random access memory cell with dual stress liner 有权
标题翻译：具有双重应力衬垫的非对称静态随机存取存储单元
公开(公告)号：US08467233B2
公开(公告)日：2013-06-18
申请号：US13154225
申请日：2011-06-06
申请人： Shaofeng Yu , Wah Kit Loh
发明人： Shaofeng Yu , Wah Kit Loh
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L21/823807 , H01L27/0207 , H01L27/1104 , H01L29/7843
摘要： A solid-state memory in which each memory cell is constructed of complementary metal-oxide-semiconductor (CMOS) inverters implemented with dual stress liner (DSL) technology. Asymmetry is incorporated into each memory cell by constructing one of the inverter transistors or the pass-gate transistor using the stress liner with opposite stress characteristics from its opposing counterpart. For example, both of the p-channel load transistors and one of the n-channel driver transistors in each memory cell may be constructed with a compressive nitride liner layer while the other driver transistor is constructed with a tensile nitride liner layer. In another implementation, one of the n-channel pass-gate transistors is constructed with a compressive nitride liner layer while the other pass-gate transistor is constructed with a tensile nitride liner layer. Improved cell stability due to the resulting asymmetric behavior is implemented in a cost-free manner.
摘要翻译：一种固态存储器，其中每个存储单元由用双重应力衬垫（DSL）技术实现的互补金属氧化物半导体（CMOS）反相器构成。通过使用具有相反应力特性的应力衬垫从其相对的对应物构造逆变器晶体管或通过栅极晶体管中的一个，将不对称结合到每个存储单元中。例如，p沟道负载晶体管和每个存储单元中的n沟道驱动晶体管中的一个可以由压缩氮化物衬垫层构成，而另一个驱动晶体管由氮化物衬垫层构成。在另一实现中，n沟道栅极晶体管中的一个由压缩氮化物衬垫层构成，而另一个栅极晶体管由拉伸氮化物衬垫层构成。由于产生的不对称行为而改善的细胞稳定性以无成本的方式实现。

4. 发明申请

US20120307550A1 Asymmetric Static Random Access Memory Cell with Dual Stress Liner 有权
标题翻译：具有双重应力衬垫的非对称静态随机存取存储单元
公开(公告)号：US20120307550A1
公开(公告)日：2012-12-06
申请号：US13154225
申请日：2011-06-06
申请人： Shaofeng Yu , Wah Kit Loh
发明人： Shaofeng Yu , Wah Kit Loh
IPC分类号： G11C11/34 , H01L21/8244
CPC分类号： G11C11/412 , H01L21/823807 , H01L27/0207 , H01L27/1104 , H01L29/7843
摘要： A solid-state memory in which each memory cell is constructed of complementary metal-oxide-semiconductor (CMOS) inverters implemented with dual stress liner (DSL) technology. Each memory cell includes a pair of cross-coupled CMOS inverters, and corresponding pass gates for coupling the cross-coupled storage nodes to first and second bit lines. Asymmetry is incorporated into each memory cell by constructing one of the inverter transistors or the pass-gate transistor using the stress liner with opposite stress characteristics from its opposing counterpart. For example, both of the p-channel load transistors and one of the n-channel driver transistors in each memory cell may be constructed with a compressive nitride liner layer while the other driver transistor is constructed with a tensile nitride liner layer. In another implementation, one of the n-channel pass-gate transistors is constructed with a compressive nitride liner layer while the other pass-gate transistor is constructed with a tensile nitride liner layer. Improved cell stability due to the resulting asymmetric behavior is implemented in a cost-free manner.
摘要翻译：一种固态存储器，其中每个存储单元由用双重应力衬垫（DSL）技术实现的互补金属氧化物半导体（CMOS）反相器构成。每个存储单元包括一对交叉耦合CMOS反相器，以及用于将交叉耦合的存储节点耦合到第一和第二位线的相应的通过门。通过使用具有相反应力特性的应力衬垫从其相对的对应物构造逆变器晶体管或通过栅极晶体管中的一个，将不对称结合到每个存储单元中。例如，p沟道负载晶体管和每个存储单元中的n沟道驱动晶体管中的一个可以由压缩氮化物衬垫层构成，而另一个驱动晶体管由氮化物衬垫层构成。在另一实现中，n沟道栅极晶体管中的一个由压缩氮化物衬垫层构成，而另一个栅极晶体管由拉伸氮化物衬垫层构成。由于产生的不对称行为而改善的细胞稳定性以无成本的方式实现。

5. 发明授权

US08542545B2 Repairing soft failures in memory cells in SRAM arrays 有权
标题翻译：修复SRAM阵列存储单元中的软故障
公开(公告)号：US08542545B2
公开(公告)日：2013-09-24
申请号：US13070799
申请日：2011-03-24
申请人： Wah Kit Loh , Beena Pious
发明人： Wah Kit Loh , Beena Pious
IPC分类号： G11C29/00
CPC分类号： G11C11/417 , G11C11/412 , G11C29/52
摘要： An embodiment of the invention provides a method of repairing soft failures in memory cells of an SRAM array. The SRAM array is tested to determine the location and type of soft failures in the memory cells. An assist circuit is activated that changes a voltage in a group of memory cells with the same type of soft failure. The change in voltage created by the assist circuit repairs the soft failures in the group. The group may be a word line or a bit line. The type of soft failures includes a failure during a read of a memory cell and a failure during the write of a memory cell.
摘要翻译：本发明的实施例提供了修复SRAM阵列的存储单元中的软故障的方法。测试SRAM阵列以确定存储器单元中软故障的位置和类型。激活辅助电路，其改变具有相同类型的软故障的一组存储器单元中的电压。辅助电路产生的电压变化会修复组中的软故障。该组可以是字线或位线。软故障的类型包括在存储器单元的读取期间的故障和在存储器单元写入期间的故障。

6. 发明申请

US20130182490A1 Static Random Access Memory Cell with Single-Sided Buffer and Asymmetric Construction 有权
标题翻译：具有单边缓冲和静态随机存取存储单元的非对称结构
公开(公告)号：US20130182490A1
公开(公告)日：2013-07-18
申请号：US13477901
申请日：2012-05-22
申请人： Xiaowei Deng , Wah Kit Loh , Anand Seshadri , Zhonghai Shi
发明人： Xiaowei Deng , Wah Kit Loh , Anand Seshadri , Zhonghai Shi
IPC分类号： G11C11/40 , H01L21/82
CPC分类号： G11C11/413 , G11C11/412 , H01L27/1104
摘要： Balanced electrical performance in a static random access memory (SRAM) cell with an asymmetric context such as a buffer circuit. Each memory cell includes a circuit feature, such as a read buffer, that has larger transistor sizes and features than the other transistors within the cell, and in which the feature asymmetrical influences the smaller cell transistors. For best performance, pairs of cell transistors are to be electrically matched with one another. One or more of the cell transistors nearer to the asymmetric feature are constructed differently, for example with different channel width, channel length, or net channel dopant concentration, to compensate for the proximity effects of the asymmetric feature.
摘要翻译：在具有不对称上下文（例如缓冲电路）的静态随机存取存储器（SRAM）单元中的平衡电性能。每个存储单元包括诸如读缓冲器的电路特征，其具有比单元内的其它晶体管更大的晶体管尺寸和特征，并且其中特征不对称影响较小单元晶体管。为了获得最佳性能，单元晶体管对将彼此电气匹配。更接近不对称特征的单元晶体管中的一个或多个不同地构成，例如具有不同的沟道宽度，沟道长度或净沟道掺杂剂浓度，以补偿不对称特征的邻近效应。

7. 发明授权

US07924640B2 Method for memory cell characterization using universal structure 有权
标题翻译：使用通用结构记忆细胞表征的方法
公开(公告)号：US07924640B2
公开(公告)日：2011-04-12
申请号：US11945469
申请日：2007-11-27
申请人： Xiaowei Deng , Wah Kit Loh
发明人： Xiaowei Deng , Wah Kit Loh
IPC分类号： G11C29/00
CPC分类号： G11C29/006 , G11C11/413 , G11C2029/0403 , H01L22/34 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L27/11807
摘要： A test method includes providing an integrated circuit, where the integrated circuit includes a memory base cell, where the memory base cell includes a first storage node set, a second storage node set, a set of other nodes, and a set of circuit elements each having a plurality of terminals, where the set of other nodes includes a first data node for accessing the first storage node set, a first access control node for controlling the access of the first storage node set, a first supply node for supplying the first storage node set, and a second supply node for supplying the second storage node set, where the first and second supply nodes are of the same sinking or sourcing type. The method further includes conducting a circuit element test on a circuit element in the set of circuit elements, where in the circuit element test the first and second supply nodes are not connected together, each terminal of the circuit element is directly forced with an electrical quantity, and an electrical quantity is directly measured from a terminal of the circuit element. Further, the method includes conducting at least one of a static noise margin test or a full cell test on the memory base cell.
摘要翻译：测试方法包括提供集成电路，其中集成电路包括存储器基本单元，其中存储器基本单元包括第一存储节点集合，第二存储节点集合，一组其他节点以及各组电路元件具有多个终端，其中所述一组其他节点包括用于访问所述第一存储节点集的第一数据节点，用于控制所述第一存储节点集合的访问的第一访问控制节点，用于提供所述第一存储节点集合，以及用于提供第二存储节点集合的第二供应节点，其中第一和第二供应节点具有相同的下沉或采购类型。该方法还包括对电路元件集合中的电路元件进行电路元件测试，其中在电路元件测试中，第一和第二供电节点未连接在一起，电路元件的每个端子被直接用电量强制，并且从电路元件的端子直接测量电量。此外，该方法包括在存储器基本单元上执行静态噪声容限测试或全单元测试中的至少一个。

8. 发明申请

US20110051539A1 Method and structure for SRAM VMIN/VMAX measurement 有权
标题翻译： SRAM VMIN / VMAX测量的方法和结构
公开(公告)号：US20110051539A1
公开(公告)日：2011-03-03
申请号：US12584219
申请日：2009-09-01
申请人： Xiaowei Deng , Wah Kit Loh
发明人： Xiaowei Deng , Wah Kit Loh
IPC分类号： G11C29/00 , G11C7/10 , G11C11/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/5004
摘要： A parametric test circuit is disclosed (FIG. 8B). The test circuit includes a latch circuit having true and complementary terminals. A first access transistor (206) has a current path connected between the true terminal and a first access terminal (214) and has a first control terminal. A second access transistor (208) has a current path connected between the complementary terminal and a second access terminal (216) and has a second control terminal connected to the first control terminal. A multiplex circuit (804) is arranged to apply a first voltage (VDD1) to the first power supply terminal in response to a first state of a select signal (SEL) and to apply a second voltage (VDD2) to the first power supply terminal in response to a second state of a select signal.
摘要翻译：公开了参数测试电路（图8B）。测试电路包括具有真实和互补端子的锁存电路。第一存取晶体管（206）具有连接在真实终端和第一接入终端（214）之间的电流路径，并且具有第一控制终端。第二存取晶体管（208）具有连接在互补端子和第二接入端子（216）之间的电流路径，并且具有连接到第一控制端子的第二控制端子。复用电路（804）被配置为响应于选择信号（SEL）的第一状态向第一电源端子施加第一电压（VDD1），并且向第一电源端子施加第二电压（VDD2）响应于选择信号的第二状态。

9. 发明授权

US07821816B2 Method for constructing Shmoo plots for SRAMs 有权
标题翻译：构建SRAM的Shmoo图的方法
公开(公告)号：US07821816B2
公开(公告)日：2010-10-26
申请号：US12401181
申请日：2009-03-10
申请人： Xiaowei Deng , Theodore W. Houston , Wah Kit Loh
发明人： Xiaowei Deng , Theodore W. Houston , Wah Kit Loh
IPC分类号： G11C11/00
CPC分类号： G11C29/44 , G11C11/41 , G11C29/023 , G11C29/028 , G11C29/12005 , G11C29/50 , G11C2029/0405 , G11C2029/1202
摘要： A method of preparing Shmoo plots where both the number of failures and also the failure type is specified at each test voltage measurement point. A method that uses the operational SRAM array circuitry to determine the type of failure that may have occurred at each test voltage measurement point.
摘要翻译：在每个测试电压测量点指定故障次数和故障类型的Shmoo图的准备方法。一种使用操作SRAM阵列电路来确定每个测试电压测量点可能发生的故障类型的方法。

10. 发明申请

US20080062746A1 SRAM static noise margin test structure suitable for on chip parametric measurements 有权
标题翻译： SRAM静态噪声容限测试结构适用于片上参数测量
公开(公告)号：US20080062746A1
公开(公告)日：2008-03-13
申请号：US11519312
申请日：2006-09-12
申请人： Wah Kit Loh , Donald James Redwine
发明人： Wah Kit Loh , Donald James Redwine
IPC分类号： G11C11/00 , G11C7/02 , G11C29/00 , G11C7/00
CPC分类号： G11C7/02 , G11C11/41 , G11C29/24 , G11C29/50 , G11C2029/5002
摘要： A set of memory cell test structures and a method are disclosed for assessment of the static noise margin (SNM) of a memory cell or an array of such cells, for example, of SRAM cells of an integrated circuit device, using discrete point measurement structures provided either on-chip or within the scribe lines. In one embodiment, the set of memory structures comprises first and second test structures, individually comprising a memory cell, having one or more left and right half-bit test structures having hard-wired connections between select nodes of each memory cell half-bit and one or more voltage supplies. The half-bits of the first test structure are configured for measuring respective left and right standby SNM values, and the half-bits of the second test structure are configured for measuring respective left and right cell ratio values at respective output nodes of the structures, using applied supply voltages for on-chip assessment of the static noise margin of the memory cells. The method applies the supply voltages to select nodes of the test structures, measures left and right standby SNM values at a first test structure, measures left and right cell ratio values at a second test structure, determines a first difference between the left half-bit standby SNM value and the right half-bit cell ratio value, determines a second difference between the right half-bit standby SNM value and the left half-bit cell ratio value, and determines a smaller one of the first and second difference values proportional to an SNM value of the cell.
摘要翻译：公开了一组存储器单元测试结构和方法，用于评估存储器单元或诸如集成电路器件的SRAM单元的这种单元阵列的静态噪声容限（SNM），使用离散点测量结构提供在片上或在划线内。在一个实施例中，该组存储器结构包括第一和第二测试结构，其独立地包括存储单元，其具有一个或多个左和右半位测试结构，每个测试结构在每个存储单元半位的选择节点之间具有硬连接，一个或多个电压源。第一测试结构的半位被配置用于测量相应的左和右备用SNM值，并且第二测试结构的半位被配置用于测量结构的各个输出节点处的相应左和右单元比值，使用应用的电源电压来对存储器单元的静态噪声容限进行片上评估。该方法将电源电压施加到测试结构的选择节点，在第一测试结构处测量左和右备用SNM值，测量第二测试结构处的左和右单元比率值，确定左半位待机SNM值和右半位单元比率值确定右半位待机SNM值和左半位单元比率值之间的第二差，并且确定与第一和第二差值成比例的较小的一个单元格的SNM值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式