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1. 发明授权

US09076668B2 Method of manufacturing the trench of U-shape 有权
标题翻译：制造U型沟槽的方法
公开(公告)号：US09076668B2
公开(公告)日：2015-07-07
申请号：US14070060
申请日：2013-11-01
申请人： Shanghai Huali Microelectronics Corporation
发明人： XuBin Jing , Fang Li , WenYan Liu
IPC分类号： H01L21/8238 , H01L29/08 , H01L29/66 , H01L21/4757 , H01L27/092
CPC分类号： H01L29/0847 , H01L21/47576 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/092 , H01L29/66477 , H01L29/66636 , H01L29/78
摘要： The present invention relates to the manufacture of CMOS semiconductor device. This invention includes: Step S1, a layer of silicon oxide is deposited covering the surface of the polysilicon gates and the exposed upper surface of the silicon substrate, the silicon oxide layer is removed on the upper surface of the exposed silicon substrate, and then the barrier layer is formed at the surface of the polysilicon gates; Step S2, the ions are implanted into the exposed substrate, and then several doped silicon regions are formed in the silicon substrate; Step S3, the doped silicon regions are etched to form the trench of U-shape, then the barrier layer is removed. The present invention protects the polysilicon gate and the substrate during the process of forming the trench. The rate of etching is increased and the productivity is improved and it is possible to control the depth of the U-shaped trench.
摘要翻译：本发明涉及CMOS半导体器件的制造。本发明包括：步骤S1，沉积覆盖多晶硅栅极的表面和硅衬底的暴露的上表面的氧化硅层，在暴露的硅衬底的上表面上去除氧化硅层，然后阻挡层形成在多晶硅栅极的表面; 步骤S2，将离子注入暴露的衬底中，然后在硅衬底中形成多个掺杂的硅区; 步骤S3，蚀刻掺杂的硅区域以形成U形沟槽，然后去除阻挡层。本发明在形成沟槽的过程中保护多晶硅栅极和衬底。蚀刻速率提高，生产率提高，并且可以控制U形沟槽的深度。

2. 发明申请

US20140273388A1 METHOD OF MANUFACTURING THE TRENCH OF U-SHAPE 有权
标题翻译：制造U形纹的方法
公开(公告)号：US20140273388A1
公开(公告)日：2014-09-18
申请号：US14070060
申请日：2013-11-01
申请人： Shanghai Huali Microelectronics Corporation
发明人： XuBin Jing , Fang Li , WenYan Liu
IPC分类号： H01L29/08 , H01L29/66
CPC分类号： H01L29/0847 , H01L21/47576 , H01L21/823807 , H01L21/823814 , H01L21/823878 , H01L27/092 , H01L29/66477 , H01L29/66636 , H01L29/78
摘要： The present invention relates to the manufacture of CMOS semiconductor device. This invention includes: Step S1, a layer of silicon oxide is deposited covering the surface of the polysilicon gates and the exposed upper surface of the silicon substrate, the silicon oxide layer is removed on the upper surface of the exposed silicon substrate, and then the barrier layer is formed at the surface of the polysilicon gates; Step S2, the ions are implanted into the exposed substrate, and then several doped silicon regions are formed in the silicon substrate; Step S3, the doped silicon regions are etched to form the trench of U-shape, then the barrier layer is removed. The present invention protects the polysilicon gate and the substrate during the process of forming the trench. The rate of etching is increased and the productivity is improved and it is possible to control the depth of the U-shaped trench.
摘要翻译：本发明涉及CMOS半导体器件的制造。本发明包括：步骤S1，沉积覆盖多晶硅栅极的表面和硅衬底的暴露的上表面的氧化硅层，在暴露的硅衬底的上表面上去除氧化硅层，然后阻挡层形成在多晶硅栅极的表面; 步骤S2，将离子注入暴露的衬底中，然后在硅衬底中形成多个掺杂的硅区; 步骤S3，蚀刻掺杂的硅区域以形成U形沟槽，然后去除阻挡层。本发明在形成沟槽的过程中保护多晶硅栅极和衬底。蚀刻速率提高，生产率提高，并且可以控制U形沟槽的深度。

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