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1. 发明申请

US20210036117A1 Memory And Method For Forming The Same 有权
公开(公告)号：US20210036117A1
公开(公告)日：2021-02-04
申请号：US16788943
申请日：2020-02-12
申请人： Shanghai Huahong Grace Semiconductor Manufacturing Corporation
发明人： Tao YU
IPC分类号： H01L29/423 , H01L29/788 , H01L29/78 , H01L21/28 , H01L29/66 , H01L21/265 , H01L21/768 , H01L23/535
摘要： The present disclosure provides a memory and a method for forming the memory. The method includes: providing a base with a first fin and a second fin formed thereon, wherein the first fin comprises an erasing region and a floating gate region on both sides of the erasing region, and a sacrificial layer is disposed on a surface of the erasing region and a surface of the second fin; forming a floating gate structure across the floating gate region on the base; forming a first sidewall film on a top surface and sidewall surfaces of the floating gate structure on the base; removing the sacrificial layer, and forming an opening in the floating gate structure and the first sidewall film; and forming an erasing gate structure in the opening. The memory formed by the method has good performance.

2. 发明申请

US20210296330A1 Memory and Method for Forming the Same 有权
公开(公告)号：US20210296330A1
公开(公告)日：2021-09-23
申请号：US16909619
申请日：2020-06-23
申请人： Shanghai Huahong Grace Semiconductor Manufacturing Corporation
发明人： Tao YU
IPC分类号： H01L27/11517 , H01L29/788 , G11C5/02 , H01L29/66
摘要： The present disclosure provides a memory and a method for forming the memory. The memory includes: a substrate including a first storage area and a second storage area; a source region disposed in the substrate between the first storage area and the second storage area; a first drain region and a second drain region in the substrate on both sides of the first storage area and the second storage area; a first storage structure disposed on the first storage area, including a first storage unit, a second storage unit, and a first word line gate; and a second storage structure disposed on the second storage area, including a third storage unit, a fourth storage unit, and a second word line gate. The memory can obtain an improved performance.

3. 发明申请

US20210358927A1 Memory And Method For Forming The Same 有权
公开(公告)号：US20210358927A1
公开(公告)日：2021-11-18
申请号：US17012391
申请日：2020-09-04
申请人： Shanghai Huahong Grace Semiconductor Manufacturing Corporation
发明人： Xufeng WANG , Tao YU , Binghan LI
IPC分类号： H01L27/11517 , G11C16/08
摘要： The present disclosure provides a memory and a method for forming the memory. The memory includes: a substrate including an erase region and a floating gate region, wherein the floating gate region is adjacent to the erase region, and both sides of the erase region are disposed with the floating gate region; a floating gate structure disposed on the floating gate region; a control gate structure disposed on the floating gate structure; and a word line gate structure disposed on the substrate on both sides of the erase region and the floating gate region, wherein the word line gate structure is in contact with a part of the control gate structure, and a first sidewall is disposed between the floating gate structure and the word line gate structure. The memory has good performance.

4. 发明申请

US20150255476A1 EEPROM DEVICE AND FORMING METHOD AND ERASING METHOD THEREOF 有权
标题翻译： EEPROM设备及其形成方法及其擦除方法
公开(公告)号：US20150255476A1
公开(公告)日：2015-09-10
申请号：US14587472
申请日：2014-12-31
申请人： Shanghai Huahong Grace Semiconductor Manufacturing Corporation
发明人： Tao YU
IPC分类号： H01L27/115 , H01L29/788 , H01L29/66 , G11C16/14
CPC分类号： H01L27/11521 , G11C16/0458 , G11C16/14 , H01L27/11519 , H01L29/66825 , H01L29/788
摘要： An EEPROM device, a forming method thereof, and a method for implementing an erase operation to the device are provided. The EEPROM device includes: a semiconductor substrate having active regions therein; a word line disposed on a first active region; float gate dielectric layers disposed on second active regions; float gates disposed on the float gate dielectric layers, wherein each of the float gates has a width larger than that of the second active region; control gates disposed on control gate dielectric layers which are disposed on the float gates; an isolation oxide layer disposed between the word line and the float gates along with the control gates; and bit line doping regions disposed on third active regions. Accordingly, an erase operation can be implemented from a bit line, and coupling ratios of a float gate to a control gate and to a bit line doping region can be improved.
摘要翻译：提供了一种EEPROM器件，其形成方法以及用于实现对器件的擦除操作的方法。 EEPROM器件包括：其中具有有源区的半导体衬底; 设置在第一有源区上的字线; 设置在第二有源区上的浮栅绝缘层; 浮置栅极设置在浮动栅极电介质层上，其中每个浮动栅极的宽度大于第二有源区域的宽度; 布置在控制栅极电介质层上的控制门设置在浮动栅上; 与控制栅极一起设置在字线和浮动栅之间的隔离氧化物层; 以及位于第三有源区上的位线掺杂区。因此，可以从位线实现擦除操作，并且可以提高浮动栅极与控制栅极和位线掺杂区域的耦合比。

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