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1. 发明授权

US06729935B2 Method and system for in-situ monitoring of mixing ratio of high selectivity slurry 失效
公开(公告)号：US06729935B2
公开(公告)日：2004-05-04
申请号：US10170674
申请日：2002-06-13
申请人： Shang-Ting Tsai , Ping Chuang , Henry Lo , Chao-Jung Chang , Ping-Hsu Chen , Yu-Liang Lin , Yu-Huei Chen , Ai-Sen Liu , Syun-Ming Jang
发明人： Shang-Ting Tsai , Ping Chuang , Henry Lo , Chao-Jung Chang , Ping-Hsu Chen , Yu-Liang Lin , Yu-Huei Chen , Ai-Sen Liu , Syun-Ming Jang
IPC分类号： B24B4900
CPC分类号： B24B57/02 , B24B37/042 , B24B49/12
摘要： A method and system for monitoring the quality of a slurry utilized in a chemical mechanical polishing operation. A slurry is generally delivered through a tubular path during a chemical mechanical polishing operation. A laser light is generally transmitted from a laser light source, such that the laser light comes into contact with the slurry during the chemical mechanical polishing operation. The laser light can then be detected, after the laser light comes into contact with the slurry to thereby monitor the quality of the slurry utilized during the chemical mechanical polishing operation. The laser light that comes into contact with the slurry can be also be utilized to monitor a mixing ratio associated with the slurry.

2. 发明授权

US06884149B2 Method and system for in-situ monitoring of mixing ratio of high selectivity slurry 失效
标题翻译：高选择性浆料混合比的现场监测方法和系统
公开(公告)号：US06884149B2
公开(公告)日：2005-04-26
申请号：US10833720
申请日：2004-04-27
申请人： Shang-Ting Tsai , Ping Chuang , Henry Lo , Chao-Jung Chang , Ping-Hsu Chen , Yu-Liang Lin , Yu-Huei Chen , Ai-Sen Liu , Syun-Ming Jang
发明人： Shang-Ting Tsai , Ping Chuang , Henry Lo , Chao-Jung Chang , Ping-Hsu Chen , Yu-Liang Lin , Yu-Huei Chen , Ai-Sen Liu , Syun-Ming Jang
IPC分类号： B24B37/04 , B24B49/12 , B24B1/00
CPC分类号： B24B57/02 , B24B37/042 , B24B49/12
摘要： A method and system for monitoring the quality of a slurry utilized in a chemical mechanical polishing operation. A slurry is generally delivered through a tubular path during a chemical mechanical polishing operation. A laser light is generally transmitted from a laser light source, such that the laser light comes into contact with the slurry during the chemical mechanical polishing operation. The laser light can then be detected, after the laser light comes into contact with the slurry to thereby monitor the quality of the slurry utilized during the chemical mechanical polishing operation. The laser light that comes into contact with the slurry can be also be utilized to monitor a mixing ratio associated with the slurry.
摘要翻译：一种用于监测在化学机械抛光操作中使用的浆料的质量的方法和系统。在化学机械抛光操作期间，浆料通常通过管状路径输送。激光通常从激光源传输，使得激光在化学机械抛光操作期间与浆料接触。然后可以在激光与浆料接触之后检测激光，从而监测在化学机械抛光操作期间所利用的浆料的质量。与浆料接触的激光也可用于监测与浆料相关的混合比例。

3. 发明授权

US07083495B2 Advanced process control approach for Cu interconnect wiring sheet resistance control 失效
标题翻译： Cu互连布线电阻控制的先进工艺控制方法
公开(公告)号：US07083495B2
公开(公告)日：2006-08-01
申请号：US10723236
申请日：2003-11-26
申请人： Chun Hsien Lin , Ai-Sen Liu , Sunny Wu , Yu-Liang Lin , Henry Lo , Mei-Sheng Zhou
发明人： Chun Hsien Lin , Ai-Sen Liu , Sunny Wu , Yu-Liang Lin , Henry Lo , Mei-Sheng Zhou
IPC分类号： B24B49/00 , B24B1/00
CPC分类号： B24B51/00 , B24B37/042 , G05B13/024 , H01L21/31053 , H01L21/3212
摘要： A wafer based APC method for controlling an oxide (Cu, or TaN) polish step is described and combines a feed forward model that compensates for incoming wafer variations with a feed backward model which compensates for CMP variations. The method is geared toward minimizing Rs 3σ variations. A Rs target value is inputted with metrology data from previous processes that affects the width and thickness of the copper layer. A copper thickness target and polish time for the first wafer is determined. Post CMP measurement data of the first wafer is used to modify the polish rate with a disturbance factor and an updated polish time is computed for subsequent wafers. The CMP recipe for each wafer is adjusted with metrology data and post CMP measurements. The APC method is successful in controlling copper Rs variations for the 90 nm technology node and is independent of copper pattern density.
摘要翻译：描述了用于控制氧化物（Cu或TaN）抛光步骤的基于晶圆的APC方法，并且组合了用于补偿进入晶片变化的前馈模型与补偿CMP变化的馈送反向模型。该方法面向最小化Rs 3sigma变化。输入Rs目标值，其中来自先前工艺的测量数据影响铜层的宽度和厚度。确定第一晶片的铜厚度目标和抛光时间。第一晶片的CMP后测量数据被用于利用干扰因子修改抛光速率，并且为随后的晶片计算更新的抛光时间。每个晶片的CMP配方用测量数据和后CMP测量进行调整。 APC方法成功地控制了90nm技术节点的铜Rs变化，并且与铜图案密度无关。

4. 发明申请

US20050282396A1 Micro-etching method to replicate alignment marks for semiconductor wafer photolithography 有权
标题翻译：用于复制半导体晶片光刻的对准标记的微蚀刻方法
公开(公告)号：US20050282396A1
公开(公告)日：2005-12-22
申请号：US10872238
申请日：2004-06-18
申请人： Yu-Liang Lin , Henry Lo , Chung-Long Chang , Gorge Huang , Tony Lu , Gnesh Yeh , Candy Liang , Chun-Hsien Lin , Mei Sheng Zhou , Sunny Wu , Ai-Sen Liu , Cheng-Lin Huang , Li-Jui Chen , Shih Wang
发明人： Yu-Liang Lin , Henry Lo , Chung-Long Chang , Gorge Huang , Tony Lu , Gnesh Yeh , Candy Liang , Chun-Hsien Lin , Mei Sheng Zhou , Sunny Wu , Ai-Sen Liu , Cheng-Lin Huang , Li-Jui Chen , Shih Wang
IPC分类号： H01L21/00 , H01L21/302 , H01L21/311 , H01L21/336 , H01L21/461 , H01L23/544
CPC分类号： H01L23/544 , H01L21/31111 , H01L21/67282 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for locally etching a substrate area the method including providing a substrate comprising a process surface; depositing a material layer over the process surface; and, applying a wet etchant to cover a targeted etching portion of the process surface while excluding an adjacent surrounding area to selectively etch the material layer overlying the targeted etching portion.
摘要翻译：一种用于局部蚀刻衬底区域的方法和装置，该方法包括提供包含工艺表面的衬底; 在工艺表面上沉积材料层; 以及施加湿蚀刻剂以覆盖所述工艺表面的目标蚀刻部分，同时排除相邻的周围区域以选择性地蚀刻覆盖所述目标蚀刻部分的所述材料层。

5. 发明授权

US07338909B2 Micro-etching method to replicate alignment marks for semiconductor wafer photolithography 有权
标题翻译：用于复制半导体晶片光刻的对准标记的微蚀刻方法
公开(公告)号：US07338909B2
公开(公告)日：2008-03-04
申请号：US10872238
申请日：2004-06-18
申请人： Yu-Liang Lin , Henry Lo , Chung-Long Chang , Gorge Huang , Tony Lu , Gnesh Yeh , Candy Liang , Chun-Hsien Lin , Mei Sheng Zhou , Sunny Su , Ai-Sen Liu , Cheng-Lin Huang , Li-Jui Chen , Shih Che Wang
发明人： Yu-Liang Lin , Henry Lo , Chung-Long Chang , Gorge Huang , Tony Lu , Gnesh Yeh , Candy Liang , Chun-Hsien Lin , Mei Sheng Zhou , Sunny Su , Ai-Sen Liu , Cheng-Lin Huang , Li-Jui Chen , Shih Che Wang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L23/544 , H01L21/31111 , H01L21/67282 , H01L2223/5442 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A method and apparatus for locally etching a substrate area the method including providing a substrate comprising a process surface; depositing a material layer over the process surface; and, applying a wet etchant to cover a targeted etching portion of the process surface while excluding an adjacent surrounding area to selectively etch the material layer overlying the targeted etching portion.
摘要翻译：一种用于局部蚀刻衬底区域的方法和装置，该方法包括提供包含工艺表面的衬底; 在工艺表面上沉积材料层; 以及施加湿蚀刻剂以覆盖所述工艺表面的目标蚀刻部分，同时排除相邻的周围区域以选择性地蚀刻覆盖所述目标蚀刻部分的所述材料层。

6. 发明申请

US20050112997A1 Advanced process control approach for Cu interconnect wiring sheet resistance control 失效
标题翻译： Cu互连布线电阻控制的先进工艺控制方法
公开(公告)号：US20050112997A1
公开(公告)日：2005-05-26
申请号：US10723236
申请日：2003-11-26
申请人： Chun Lin , Ai-Sen Liu , Sunny Wu , Yu-Liang Lin , Henry Lo , Mei-Sheng Zhou
发明人： Chun Lin , Ai-Sen Liu , Sunny Wu , Yu-Liang Lin , Henry Lo , Mei-Sheng Zhou
IPC分类号： B24B37/04 , B24B51/00 , G05B13/02 , H01L21/3105 , H01L21/321 , B24B49/00 , B24B1/00
CPC分类号： B24B51/00 , B24B37/042 , G05B13/024 , H01L21/31053 , H01L21/3212
摘要： A wafer based APC method for controlling an oxide (Cu, or TaN) polish step is described and combines a feed forward model that compensates for incoming wafer variations with a feed backward model which compensates for CMP variations. The method is geared toward minimizing Rs 3σ variations. A Rs target value is inputted with metrology data from previous processes that affects the width and thickness of the copper layer. A copper thickness target and polish time for the first wafer is determined. Post CMP measurement data of the first wafer is used to modify the polish rate with a disturbance factor and an updated polish time is computed for subsequent wafers. The CMP recipe for each wafer is adjusted with metrology data and post CMP measurements. The APC method is successful in controlling copper Rs variations for the 90 nm technology node and is independent of copper pattern density.
摘要翻译：描述了用于控制氧化物（Cu或TaN）抛光步骤的基于晶圆的APC方法，并且组合了用于补偿进入晶片变化的前馈模型与补偿CMP变化的馈送反向模型。该方法面向最小化Rs 3sigma变化。输入Rs目标值，其中来自先前工艺的测量数据影响铜层的宽度和厚度。确定第一晶片的铜厚度目标和抛光时间。第一晶片的CMP后测量数据被用于利用干扰因子修改抛光速率，并且为随后的晶片计算更新的抛光时间。每个晶片的CMP配方用测量数据和后CMP测量进行调整。 APC方法成功地控制了90nm技术节点的铜Rs变化，并且与铜图案密度无关。

7. 发明申请

US20050051900A1 Method for forming dielectric barrier layer in damascene structure 失效
标题翻译：在镶嵌结构中形成介质阻挡层的方法
公开(公告)号：US20050051900A1
公开(公告)日：2005-03-10
申请号：US10657847
申请日：2003-09-09
申请人： Ai-Sen Liu , Syun-Ming Jang
发明人： Ai-Sen Liu , Syun-Ming Jang
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L23/48
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76807 , H01L21/76826 , H01L21/76831 , H01L23/5222 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating dielectric barrier layers in integrated circuit structures such as damascene structures is provided. In one embodiment, a low-k dielectric layer formed on a substrate is provided. The low-k dielectric layer has at least one opening exposing an underlying metal layer. A first silicon carbide barrier layer is formed to conformally cover the exposed surfaces of the opening. A portion of the first silicon carbide barrier layer above the low-k dielectric layer and over the bottom of the opening is converted with an oxidation treatment into a layer of silicon oxide. The silicon oxide layer is removed above the low-k dielectric layer and from the bottom of the opening. The opening is filled with a conductive layer in electrical contact with the underlying metal layer. The conductive layer is removed above the low-k dielectric layer to a predetermined depth below the low-k dielectric layer to define a recess therebelow. A second silicon carbide barrier layer is formed to cover the recess and above the low-k dielectric layer and the first silicon carbide barrier layer so as to seal the top of the structure. A portion of the second silicon carbide barrier layer above the low-k dielectric layer is converted with an oxidation treatment into a layer of silicon oxide. The layer of silicon oxide is then removed and the metal conductive layer is fully encapsulated by the silicon carbide barrier layer.
摘要翻译：提供了一种用于在诸如镶嵌结构的集成电路结构中制造介电阻挡层的方法。在一个实施例中，提供了形成在衬底上的低k电介质层。低k电介质层具有暴露下面的金属层的至少一个开口。形成第一碳化硅阻挡层以保形地覆盖开口的暴露表面。在低k电介质层上方和开口底部上的第一碳化硅阻挡层的一部分被氧化处理转化成氧化硅层。在低k电介质层上方和从开口底部除去氧化硅层。开口填充有与下面的金属层电接触的导电层。将导电层在低k电介质层上方移除到低k电介质层下方的预定深度以限定其下方的凹部。形成第二碳化硅阻挡层以覆盖凹部并且在低k电介质层和第一碳化硅阻挡层上方密封结构的顶部。将低k电介质层上方的第二碳化硅阻挡层的一部分通过氧化处理转化为氧化硅层。然后去除氧化硅层，并且金属导电层被碳化硅阻挡层完全包封。

8. 发明授权

US06895360B2 Method to measure oxide thickness by FTIR to improve an in-line CMP endpoint determination 失效
标题翻译：通过FTIR测量氧化物厚度以改进在线CMP端点测定的方法
公开(公告)号：US06895360B2
公开(公告)日：2005-05-17
申请号：US10322198
申请日：2002-12-17
申请人： Ai-Sen Liu , Syun-Ming Jang
发明人： Ai-Sen Liu , Syun-Ming Jang
IPC分类号： B24B37/04 , B24B49/12 , G01B11/06 , G01B11/02 , G01B13/02
CPC分类号： B24B37/042 , B24B49/12 , G01B11/0625
摘要： A method for determining a material layer thickness transmissive to infrared (IR) energy in a semiconductor wafer manufacturing process including providing at least one semiconductor wafer comprising an IR transmissive layer; passing IR energy through the IR transmissive layer to produce at least one Fourier transform infrared (FTIR) spectrum; and, determining an amount of the IR transmissive layer present according to an amount of IR energy absorbed by a predetermined contributing characteristic vibrational mode portion of the FTIR spectrum.
摘要翻译：一种用于确定在半导体晶片制造工艺中透射到红外（IR）能量的材料层厚度的方法，包括提供包括IR透射层的至少一个半导体晶片; 通过IR透射层传递IR能量以产生至少一个傅里叶变换红外（FTIR）光谱; 以及根据由FTIR光谱的预定贡献特征振动模式部分吸收的IR能量的量确定存在的IR透射层的量。

9. 发明申请

US20050090122A1 SIOC PROPERTIES AND ITS UNIFORMITY IN BULK FOR DAMASCENE APPLICATIONS 有权
标题翻译： SIOC属性及其在大容量应用中的均匀性
公开(公告)号：US20050090122A1
公开(公告)日：2005-04-28
申请号：US10692030
申请日：2003-10-23
申请人： Syun-Ming Jang , Chung-Chi Ko , Tien-I Bao , Lih-Ping Li , Ai-Sen Liu
发明人： Syun-Ming Jang , Chung-Chi Ko , Tien-I Bao , Lih-Ping Li , Ai-Sen Liu
IPC分类号： H01L21/316 , H01L21/768 , H01L21/31
CPC分类号： H01L21/76835 , H01L21/02126 , H01L21/022 , H01L21/02271 , H01L21/0234 , H01L21/31633 , H01L21/76801 , H01L21/76807 , H01L21/76826 , H01L21/76829
摘要： A method of forming a low-k dielectric material layer comprising the following steps. A first dielectric material sub-layer is formed over a substrate. The first dielectric material sub-layer is treated with an energy treatment to form a hardened layer on the upper surface of the first dielectric material sub-layer. A second dielectric material sub-layer is formed over the hardened layer, wherein the first dielectric sub-layer, the hardened layer and the second dielectric sub-layer comprise the low-k dielectric material layer. And a dual damascene structure and a dielectric material structure formed thereby.
摘要翻译：一种形成低k电介质材料层的方法，包括以下步骤。第一介电材料子层形成在衬底上。第一介电材料子层用能量处理处理，以在第一介电材料子层的上表面上形成硬化层。第二电介质子层形成在硬化层上，其中第一介电子层，硬化层和第二电介质子层包括低k电介质材料层。以及由此形成的双镶嵌结构和介电材料结构。

10. 发明授权

US06972253B2 Method for forming dielectric barrier layer in damascene structure 失效
公开(公告)号：US06972253B2
公开(公告)日：2005-12-06
申请号：US10657847
申请日：2003-09-09
申请人： Ai-Sen Liu , Syun-Ming Jang
发明人： Ai-Sen Liu , Syun-Ming Jang
IPC分类号： H01L21/768 , H01L23/522 , H01L23/532 , H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76807 , H01L21/76826 , H01L21/76831 , H01L23/5222 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method for fabricating dielectric barrier layers in integrated circuit structures such as damascene structures is provided. In one embodiment, a low-k dielectric layer formed on a substrate is provided. The low-k dielectric layer has at least one opening exposing an underlying metal layer. A first silicon carbide barrier layer is formed to conformally cover the exposed surfaces of the opening. A portion of the first silicon carbide barrier layer above the low-k dielectric layer and over the bottom of the opening is converted with an oxidation treatment into a layer of silicon oxide. The silicon oxide layer is removed above the low-k dielectric layer and from the bottom of the opening. The opening is filled with a conductive layer in electrical contact with the underlying metal layer. The conductive layer is removed above the low-k dielectric layer to a predetermined depth below the low-k dielectric layer to define a recess therebelow. A second silicon carbide barrier layer is formed to cover the recess and above the low-k dielectric layer and the first silicon carbide barrier layer so as to seal the top of the structure. A portion of the second silicon carbide barrier layer above the low-k dielectric layer is converted with an oxidation treatment into a layer of silicon oxide. The layer of silicon oxide is then removed and the metal conductive layer is fully encapsulated by the silicon carbide barrier layer.

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