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1. 发明授权

US08456919B1 Method and apparatus to provide data including hard bit data and soft bit data to a rank modulation decoder 有权
标题翻译：提供包括硬比特数据和软比特数据的数据到秩调制解码器的方法和装置
公开(公告)号：US08456919B1
公开(公告)日：2013-06-04
申请号：US13293988
申请日：2011-11-10
申请人： Seungjune Jeon , Sergey Anatolievich Gorobets
发明人： Seungjune Jeon , Sergey Anatolievich Gorobets
IPC分类号： G11C11/34
CPC分类号： G11C11/5642 , G06F11/1072
摘要： A method includes providing data including hard bit data and soft bit data to a rank modulation decoder.
摘要翻译：一种方法包括向秩调制解码器提供包括硬比特数据和软比特数据的数据。

2. 发明授权

US09239751B1 Compressing data from multiple reads for error control management in memory systems 有权
标题翻译：从内存系统中的错误控制管理的多个读取压缩数据
公开(公告)号：US09239751B1
公开(公告)日：2016-01-19
申请号：US13831686
申请日：2013-03-15
申请人： Xiaoheng Chen , Ying Yu Tai , Jiangli Zhu , Seungjune Jeon
发明人： Xiaoheng Chen , Ying Yu Tai , Jiangli Zhu , Seungjune Jeon
IPC分类号： G11C29/00 , G06F11/08
CPC分类号： G06F11/085
摘要： The various implementations described herein include systems, methods and/or devices that may enhance the reliability with which data can be stored in and read from a memory. Some implementations include a method of compressing a sequence of read data values into a bit-tuple of a predefined length to enable soft information decoding systems that use less power and/or less memory. In some implementations, the bit-tuple of a predefined length is produced using M single-bit buffer locations, where M corresponds to the predefined length of the bit-tuple. Some implementations utilize a collection of characterization vectors that include soft information values associated with the possible permutations of the bit-tuples. In turn, a sequence of bit-tuples is converted into a sequence of soft information values by retrieving a particular characterization vector, and selecting a respective soft information value from that characterization vector for each bit-tuple in the sequence.
摘要翻译：本文描述的各种实现方式包括可以增强数据可以存储在存储器中并从存储器读取的可靠性的系统，方法和/或设备。一些实施方案包括将读取数据值序列压缩成预定义长度的位元组的方法，以使得能够使用更少功率和/或更少存储器的软信息解码系统。在一些实现中，使用M个单比特缓冲器位置产生预定长度的比特元组，其中M对应于比特元组的预定义长度。一些实现利用包括与位元组的可能排列相关联的软信息值的表征向量集合。反过来，通过检索一个特定的特征向量，从序列中的每个比特元组的表征向量中选择一个相应的软信息值，将一个比特元组序列转换成一个软信息值序列。

3. 发明授权

US09009576B1 Adaptive LLR based on syndrome weight 有权
标题翻译：基于综合征重量的自适应LLR
公开(公告)号：US09009576B1
公开(公告)日：2015-04-14
申请号：US13831713
申请日：2013-03-15
申请人： Seungjune Jeon , Ying Tai , Jiangli Zhu , Xiaoheng Chen
发明人： Seungjune Jeon , Ying Tai , Jiangli Zhu , Xiaoheng Chen
IPC分类号： H03M13/00 , G11C29/00 , G06F11/10 , H03M13/11 , H03M13/45
CPC分类号： G06F11/1068 , H03M13/1108 , H03M13/1111 , H03M13/3715 , H03M13/45
摘要： Systems, methods and/or devices that enhance the reliability with which data can be stored in and read from a memory utilize an error indicator to adaptively determine the soft information values used for decoding. For example, in some implementations, the method includes selecting a first set of one or more soft information values and receiving a read data command. The method further includes responding to the read data command by initiating performance of a data access operation to access data in a storage medium, the data access operation producing a syndrome weight; determining a first indicator based at least in part on the syndrome weight; based on the first indicator, selecting a second set of one or more soft information values; and decoding data obtained from the data access operation using the second set of one or more soft information values to produce a result.
摘要翻译：提高数据可以存储在存储器中并从存储器读取的可靠性的系统，方法和/或设备利用错误指示符来自适应地确定用于解码的软信息值。例如，在一些实现中，该方法包括选择一个或多个软信息值的第一组并接收读取数据命令。该方法还包括响应于读取数据命令，通过启动数据访问操作的性能来访问存储介质中的数据，产生校正子权重的数据访问操作; 至少部分地基于所述综合征权重来确定第一指示符; 基于所述第一指示符，选择第二组一个或多个软信息值; 以及使用所述第二组一个或多个软信息值对从所述数据访问操作获得的数据进行解码以产生结果。

4. 发明授权

US08788889B2 Bit stream aliasing in memory system with probabilistic decoding 有权
标题翻译：具有概率解码的存储器系统中的比特流混叠
公开(公告)号：US08788889B2
公开(公告)日：2014-07-22
申请号：US13304272
申请日：2011-11-23
申请人： Seungjune Jeon , Steven Cheng
发明人： Seungjune Jeon , Steven Cheng
IPC分类号： G06F11/00 , G06F11/10 , G06F13/14 , H04L1/00
CPC分类号： G06F11/1048 , G06F13/14 , H04L1/0061
摘要： An aliasing module is defined and connected to receive a first bit stream to be transmitted over a data bus from a memory to an external controller of the memory. The aliasing module is defined and connected to alias the first bit stream as a second bit stream and transmit the second bit stream over the data bus in lieu of the first bit stream. A de-aliasing module is defined and connected to receive the second bit stream from the data bus at the external controller. The de-aliasing module is defined and connected to de-alias the received second bit stream back to the first bit stream and provide the first bit stream to the external controller for processing.
摘要翻译：定义并连接混叠模块以接收要通过数据总线从存储器向存储器的外部控制器发送的第一位流。将混叠模块定义并连接到第一比特流的别名作为第二比特流，并且通过数据总线传送第二比特流代替第一比特流。解除混叠模块被定义和连接以在外部控制器处从数据总线接收第二位流。去混叠模块被定义和连接以将接收到的第二比特流解复用回第一比特流，并将第一比特流提供给外部控制器进行处理。

5. 发明授权

US08683297B2 Systems and methods of generating a replacement default read threshold 有权
标题翻译：生成替换默认读取阈值的系统和方法
公开(公告)号：US08683297B2
公开(公告)日：2014-03-25
申请号：US13287299
申请日：2011-11-02
申请人： Seungjune Jeon , Steven Cheng
发明人： Seungjune Jeon , Steven Cheng
IPC分类号： G11C29/00
CPC分类号： G11C16/26 , G11C16/349
摘要： A method includes generating a replacement default read threshold at least partially based on a default read threshold and on an updated read threshold. The method also includes sending the replacement default read threshold to the memory.
摘要翻译：一种方法包括至少部分地基于默认读取阈值和更新的读取阈值来生成替换默认读取阈值。该方法还包括将替换的默认读取阈值发送到存储器。

6. 发明申请

US20130132798A1 Bit Stream Aliasing in Memory System with Probabilistic Decoding 有权
标题翻译：具有概率解码的存储器系统中的比特流混叠
公开(公告)号：US20130132798A1
公开(公告)日：2013-05-23
申请号：US13304272
申请日：2011-11-23
申请人： Seungjune Jeon , Steven Cheng
发明人： Seungjune Jeon , Steven Cheng
IPC分类号： G06F11/10
CPC分类号： G06F11/1048 , G06F13/14 , H04L1/0061
摘要： An aliasing module is defined and connected to receive a first bit stream to be transmitted over a data bus from a memory to an external controller of the memory. The aliasing module is defined and connected to alias the first bit stream as a second bit stream and transmit the second bit stream over the data bus in lieu of the first bit stream. A de-aliasing module is defined and connected to receive the second bit stream from the data bus at the external controller. The de-aliasing module is defined and connected to de-alias the received second bit stream back to the first bit stream and provide the first bit stream to the external controller for processing.
摘要翻译：定义并连接混叠模块以接收要通过数据总线从存储器向存储器的外部控制器发送的第一位流。将混叠模块定义并连接到第一比特流的别名作为第二比特流，并且通过数据总线传送第二比特流代替第一比特流。解除混叠模块被定义和连接以在外部控制器处从数据总线接收第二位流。去混叠模块被定义和连接以将接收到的第二比特流解复用回第一比特流，并将第一比特流提供给外部控制器进行处理。

7. 发明授权

US08811081B2 Systems and methods of updating read voltages in a memory 有权
标题翻译：更新存储器中的读取电压的系统和方法
公开(公告)号：US08811081B2
公开(公告)日：2014-08-19
申请号：US13316153
申请日：2011-12-09
申请人： Seungjune Jeon , Jonathan Hsu
发明人： Seungjune Jeon , Jonathan Hsu
IPC分类号： G11C5/14
CPC分类号： G11C11/5642
摘要： A method includes receiving hard bit data and soft bit data corresponding to a portion of a memory, where each storage element of the memory stores multiple bits per storage element. The hard bit data and the soft bit data is received in connection with reading a single bit of the multiple bits from each storage element in the portion of the memory based on one or more first read voltages. One or more second read voltages based on the hard bit data and the soft bit data are generated in response to a read voltage update operation. The memory reads data from the portion of the memory using the one or more second read voltages.
摘要翻译：一种方法包括接收对应于存储器的一部分的硬比特数据和软比特数据，其中存储器的每个存储元件存储每个存储元件的多个比特。基于一个或多个第一读取电压，结合从存储器部分中的每个存储元件读取多个位的单个位来接收硬比特数据和软比特数据。响应于读取电压更新操作而产生基于硬比特数据和软比特数据的一个或多个第二读取电压。存储器使用一个或多个第二读取电压从存储器的该部分读取数据。

8. 发明授权

US08644067B2 Systems and methods of decoding data using soft bits at a non-binary decoder that uses probabilistic decoding 有权
标题翻译：在使用概率解码的非二进制解码器中使用软比特解码数据的系统和方法
公开(公告)号：US08644067B2
公开(公告)日：2014-02-04
申请号：US13307779
申请日：2011-11-30
申请人： Seungjune Jeon
发明人： Seungjune Jeon
IPC分类号： G11C16/04
CPC分类号： G06F11/1072 , G11C11/5642 , G11C16/26 , G11C16/3454
摘要： A method includes reading a representation of a codeword stored in a multi-level-cell (MLC) memory by comparing cell threshold voltages in the MLC memory to hard bit thresholds to generate hard bit values and to soft bit thresholds to generate soft bit values. The hard bit values and the soft bit values are provided to a non-binary decoder that uses probabilistic decoding to obtain decoded data.
摘要翻译：一种方法包括通过将MLC存储器中的单元阈值电压与硬比特阈值进行比较来读取存储在多电平单元（MLC）存储器中的码字的表示，以产生硬比特值和软比特阈值以产生软比特值。将硬比特值和软比特值提供给使用概率解码获得解码数据的非二进制解码器。

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