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1. 发明申请

US20080242011A1 Method of fabricating non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20080242011A1
公开(公告)日：2008-10-02
申请号：US11978567
申请日：2007-10-30
申请人： Seung-hwan Song , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Jae-woong Hyun , Choong-ho Lee , Tae-hun Kim
发明人： Seung-hwan Song , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Jae-woong Hyun , Choong-ho Lee , Tae-hun Kim
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/1203
摘要： A method of fabricating a non-volatile memory device according to example embodiments may include forming a semiconductor layer on a substrate. A plurality of lower charge storing layers may be formed on a bottom surface of the semiconductor layer. A plurality of lower control gate electrodes may be formed on the plurality of lower charge storing layers. A plurality of upper charge storing layers may be formed on a top surface of the semiconductor layer. A plurality of upper control gate electrodes may be formed on the plurality of upper charge storing layers, wherein the plurality of lower and upper control gate electrodes may be arranged alternately.
摘要翻译：根据示例性实施例的制造非易失性存储器件的方法可包括在衬底上形成半导体层。多个下电荷存储层可以形成在半导体层的底表面上。可以在多个下电荷存储层上形成多个下控制栅电极。多个上电荷存储层可以形成在半导体层的顶表面上。多个上部控制栅极电极可以形成在多个上部电荷存储层上，其中多个下部和上部控制栅电极可以交替布置。

2. 发明授权

US07585755B2 Method of fabricating non-volatile memory device 有权
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US07585755B2
公开(公告)日：2009-09-08
申请号：US11978567
申请日：2007-10-30
申请人： Seung-hwan Song , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Jae-woong Hyun , Choong-ho Lee , Tae-hun Kim
发明人： Seung-hwan Song , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Jae-woong Hyun , Choong-ho Lee , Tae-hun Kim
IPC分类号： H01L21/8239 , H01L29/788 , H01L29/792 , H01L27/105
CPC分类号： H01L21/84 , H01L27/105 , H01L27/1052 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/1203
摘要： A method of fabricating a non-volatile memory device according to example embodiments may include forming a semiconductor layer on a substrate. A plurality of lower charge storing layers may be formed on a bottom surface of the semiconductor layer. A plurality of lower control gate electrodes may be formed on the plurality of lower charge storing layers. A plurality of upper charge storing layers may be formed on a top surface of the semiconductor layer. A plurality of upper control gate electrodes may be formed on the plurality of upper charge storing layers, wherein the plurality of lower and upper control gate electrodes may be arranged alternately.
摘要翻译：根据示例性实施例的制造非易失性存储器件的方法可包括在衬底上形成半导体层。多个下电荷存储层可以形成在半导体层的底表面上。可以在多个下电荷存储层上形成多个下控制栅电极。多个上电荷存储层可以形成在半导体层的顶表面上。多个上部控制栅极电极可以形成在多个上部电荷存储层上，其中多个下部和上部控制栅电极可以交替布置。

3. 发明申请

US20110194849A1 IMAGING APPARATUS 有权
标题翻译：成像设备
公开(公告)号：US20110194849A1
公开(公告)日：2011-08-11
申请号：US13008969
申请日：2011-01-19
申请人： Seung-tack Noh , Tae-hun Kim
发明人： Seung-tack Noh , Tae-hun Kim
IPC分类号： G03B15/03
CPC分类号： G03B15/05 , G03B2215/0507
摘要： An imaging apparatus including a strobo assembly capable of controlling a light emitting angle of a strobo. The imaging apparatus includes a case and a strobo assembly mated to the case and that revolves with respect to the case. The strobo assembly includes a light source that emits light; a strobo housing that accommodates the light source; a bush embedded in the strobo housing and that provides a revolution shaft of the strobo assembly; and an elastic member accommodated in the bush and that provides a predetermined elastic force so that the strobo assembly revolves with respect to the case.
摘要翻译：一种成像设备，包括能够控制闪光灯的发光角度的闪光灯组件。成像设备包括壳体和与壳体配合并且相对于壳体旋转的闪光灯组件。频闪组件包括发光的光源; 容纳光源的闪光灯壳; 嵌入闪光灯壳体中并且提供闪光灯组件的旋转轴的衬套; 以及弹性构件，其容纳在所述衬套中并且提供预定的弹力，使得所述闪光灯组件相对于所述壳体旋转。

4. 发明申请

US20090152329A1 Method and apparatus for mounting at least two types of electronic components 有权
标题翻译：用于安装至少两种类型的电子部件的方法和装置
公开(公告)号：US20090152329A1
公开(公告)日：2009-06-18
申请号：US12315341
申请日：2008-12-02
申请人： Kyeong-heon Kim , Tae-hun Kim , Dong-hee Kim
发明人： Kyeong-heon Kim , Tae-hun Kim , Dong-hee Kim
IPC分类号： B23K31/02 , B23K1/20 , B23K3/06
CPC分类号： H05K3/3484 , H05K3/1225 , H05K2201/2027 , H05K2203/1476 , Y10T29/49144
摘要： Provided is a method and apparatus for mounting a plurality of electronic components. The method comprises mounting a first electronic component on a substrate; forming a mask on the substrate to expose the first electronic component and a region of the substrate on which a solder paste is to be applied; forming a guide on a portion of the mask disposed around the first electronic component; applying the solder paste onto the substrate by using a squeezer contacting a portion of the mask disposed around the region of the substrate on which the solder paste is to be applied; removing the guide and the mask; and mounting a second electronic component on the solder paste.
摘要翻译：提供了一种用于安装多个电子部件的方法和装置。该方法包括将第一电子部件安装在基板上; 在所述基板上形成掩模以暴露所述第一电子部件和所述基板的要被施加焊膏的区域; 在设置在所述第一电子部件周围的所述掩模的一部分上形成引导件; 通过使用与设置在其上施加有焊膏的基板的区域周围的掩模的一部分接触的挤压器将焊膏施加到基板上; 去除导板和面罩; 并将第二电子部件安装在焊膏上。

5. 发明授权

US07694868B2 Method and apparatus for mounting at least two types of electronic components 有权
标题翻译：用于安装至少两种类型的电子部件的方法和装置
公开(公告)号：US07694868B2
公开(公告)日：2010-04-13
申请号：US12315341
申请日：2008-12-02
申请人： Kyeong-heon Kim , Tae-hun Kim , Dong-hee Kim
发明人： Kyeong-heon Kim , Tae-hun Kim , Dong-hee Kim
IPC分类号： B23K35/02 , H05K3/34
CPC分类号： H05K3/3484 , H05K3/1225 , H05K2201/2027 , H05K2203/1476 , Y10T29/49144
摘要： Provided is a method and apparatus for mounting a plurality of electronic components. The method comprises mounting a first electronic component on a substrate; forming a mask on the substrate to expose the first electronic component and a region of the substrate on which a solder paste is to be applied; forming a guide on a portion of the mask disposed around the first electronic component; applying the solder paste onto the substrate by using a squeezer contacting a portion of the mask disposed around the region of the substrate on which the solder paste is to be applied; removing the guide and the mask; and mounting a second electronic component on the solder paste.
摘要翻译：提供了一种用于安装多个电子部件的方法和装置。该方法包括将第一电子部件安装在基板上; 在所述基板上形成掩模以暴露所述第一电子部件和所述基板的要被施加焊膏的区域; 在设置在所述第一电子部件周围的所述掩模的一部分上形成引导件; 通过使用与设置在其上施加有焊膏的基板的区域周围的掩模的一部分接触的挤压器将焊膏施加到基板上; 去除导板和面罩; 并将第二电子部件安装在焊膏上。

6. 发明授权

US07615415B2 Vertical stack type multi-chip package having improved grounding performance and lower semiconductor chip reliability 有权
标题翻译：具有改进的接地性能和较低半导体芯片可靠性的垂直堆叠式多芯片封装
公开(公告)号：US07615415B2
公开(公告)日：2009-11-10
申请号：US11781377
申请日：2007-07-23
申请人： Heung-kyu Kwon , Tae-hun Kim , Su-chang Lee
发明人： Heung-kyu Kwon , Tae-hun Kim , Su-chang Lee
IPC分类号： H01L21/00
CPC分类号： H01L25/03 , H01L21/563 , H01L23/3128 , H01L23/3135 , H01L23/552 , H01L24/48 , H01L24/73 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/12044 , H01L2924/15311 , H01L2924/181 , H01L2924/30107 , H01L2924/3011 , H01L2924/3025 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A vertical stack type multi-chip package is provided having improved reliability by increasing the grounding performance and preventing the decrease in reliability of the multi-chip package from moisture penetration into a lower semiconductor chip. The vertical stack type multi-chip package comprises an organic substrate having a printed circuit pattern on which a semiconductor chip is mounted. A first semiconductor chip is mounted on a die bonding region of the organic substrate and is electrically connected to the organic substrate through a first wire. A metal stiffener is formed on the first semiconductor chip and connected to the organic substrate by a first ground unit around the first semiconductor chip. An encapsulant is used to seal the first semiconductor chip below the metal stiffener. A second semiconductor chip, which is larger in size than that the first semiconductor chip, is mounted on the metal stiffener and connected by a second ground unit. The second semiconductor chip is connected to the organic substrate by a second wire. A mold resin seals the second semiconductor chip and a solder ball is bonded to a solder ball pad below the organic substrate.
摘要翻译：通过提高接地性能并防止多芯片封装的湿度渗透到下半导体芯片中的可靠性降低，提供了具有提高的可靠性的垂直堆叠型多芯片封装。垂直堆叠型多芯片封装包括具有其上安装有半导体芯片的印刷电路图案的有机基板。第一半导体芯片安装在有机基板的芯片接合区域上，并通过第一导线与有机基板电连接。在第一半导体芯片上形成金属加强件，并通过第一半导体芯片周围的第一接地单元与有机基板连接。密封剂用于将金属加强件下方的第一半导体芯片密封。尺寸大于第一半导体芯片的第二半导体芯片安装在金属加强件上并通过第二接地单元连接。第二半导体芯片通过第二线连接到有机基板。模具树脂密封第二半导体芯片，焊球与有机基板下方的焊球焊盘接合。

7. 发明申请

US20120195581A1 COMPACT POP-UP CAMERA FLASHES 有权
公开(公告)号：US20120195581A1
公开(公告)日：2012-08-02
申请号：US13271545
申请日：2011-10-12
申请人： Tae-hun Kim , Seung-tack Noh
发明人： Tae-hun Kim , Seung-tack Noh
IPC分类号： G03B15/03
CPC分类号： G03B17/566 , G03B2215/0507 , G03B2215/056
摘要： Example pop-up camera flashes are disclosed. A disclosed example pop-up flash of a camera includes a supporting unit; a rotating unit, which is rotatably connected to the supporting unit and is able to rotate between a first position, at which the rotating unit is adjacent to the supporting unit, and a second poison, at which the rotating unit is apart from the supporting unit; a sliding unit, which is slidably combined with the rotating unit; a light emitting unit, which is arranged at the sliding unit; a connecting unit, of which a first end is rotatably connected to the sliding unit and a second end is rotatably connected to the supporting unit; and a driving unit, which is connected to the connecting unit and provides a driving force for rotation of the connecting unit.
摘要翻译：公开了示例性的弹出式照相机闪光。照相机的公开示例弹出闪光灯包括支撑单元; 旋转单元，其可旋转地连接到所述支撑单元，并且能够在所述旋转单元与所述支撑单元相邻的第一位置和所述第二毒物之间旋转，所述旋转单元与所述支撑单元分离， ; 滑动单元，其与所述旋转单元可滑动地组合; 布置在滑动单元处的发光单元; 连接单元，其第一端可旋转地连接到滑动单元，第二端可旋转地连接到支撑单元; 以及驱动单元，其连接到连接单元并且提供用于连接单元的旋转的驱动力。

8. 发明授权

US08170410B2 Imaging apparatus 有权
标题翻译：成像设备
公开(公告)号：US08170410B2
公开(公告)日：2012-05-01
申请号：US13008969
申请日：2011-01-19
申请人： Seung-tack Noh , Tae-hun Kim
发明人： Seung-tack Noh , Tae-hun Kim
IPC分类号： G03B15/03
CPC分类号： G03B15/05 , G03B2215/0507
摘要： An imaging apparatus including a strobo assembly capable of controlling a light emitting angle of a strobo. The imaging apparatus includes a case and a strobo assembly mated to the case and that revolves with respect to the case. The strobo assembly includes a light source that emits light; a strobo housing that accommodates the light source; a bush embedded in the strobo housing and that provides a revolution shaft of the strobo assembly; and an elastic member accommodated in the bush and that provides a predetermined elastic force so that the strobo assembly revolves with respect to the case.
摘要翻译：一种成像设备，包括能够控制闪光灯的发光角度的闪光灯组件。成像设备包括壳体和与壳体配合并且相对于壳体旋转的闪光灯组件。频闪组件包括发光的光源; 容纳光源的闪光灯壳; 嵌入闪光灯壳体中并且提供闪光灯组件的旋转轴的衬套; 以及弹性构件，其容纳在所述衬套中并且提供预定的弹力，使得所述闪光灯组件相对于所述壳体旋转。

9. 发明授权

US07928555B2 Stack semiconductor package including an interposer chip having an imposed diode or capacitor 有权
标题翻译：堆叠半导体封装包括具有施加的二极管或电容器的插入器芯片
公开(公告)号：US07928555B2
公开(公告)日：2011-04-19
申请号：US11806589
申请日：2007-06-01
申请人： Tae-hun Kim , Heung-kyu Kwon
发明人： Tae-hun Kim , Heung-kyu Kwon
IPC分类号： H01L23/48
CPC分类号： H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L24/78 , H01L24/85 , H01L25/0657 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2224/49171 , H01L2224/73265 , H01L2224/78301 , H01L2224/851 , H01L2224/859 , H01L2224/92247 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562 , H01L2225/06572 , H01L2225/06575 , H01L2225/06586 , H01L2225/06596 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/01093 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19107 , H01L2924/30105 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A stacked semiconductor package may include a wiring substrate. A first semiconductor chip may be disposed on the wiring substrate and wire-bonded to the wiring substrate. An interposer chip may be disposed on the wiring substrate and sire bonded to the wiring substrate. The interposer chip may include a circuit element and a bonding pad being electrically connected. A second semiconductor chip may be disposed on the interposer chip and wire-bonded to the interposer chip. The second semiconductor chip may be electrically connected to the wiring substrate through the interposer chip.
摘要翻译：堆叠的半导体封装可以包括布线基板。第一半导体芯片可以布置在布线基板上并且引线接合到布线基板。可以在布线基板上布置插入件芯片，并将其连接到布线基板。插入器芯片可以包括电连接的电路元件和接合焊盘。第二半导体芯片可以设置在插入器芯片上并引线接合到插入器芯片。第二半导体芯片可以通过插入器芯片电连接到布线基板。

10. 发明授权

US07541680B2 Semiconductor device package 有权
标题翻译：半导体器件封装
公开(公告)号：US07541680B2
公开(公告)日：2009-06-02
申请号：US11509641
申请日：2006-08-25
申请人： Heung-kyu Kwon , Se-nyun Kim , Tae-hun Kim , Jeong-o Ha , Hak-kyoon Byun , Sung-yong Park
发明人： Heung-kyu Kwon , Se-nyun Kim , Tae-hun Kim , Jeong-o Ha , Hak-kyoon Byun , Sung-yong Park
IPC分类号： H01L23/12 , H01L23/48
CPC分类号： H01L23/50 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/83 , H01L24/85 , H01L25/0657 , H01L2224/05553 , H01L2224/32145 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48145 , H01L2224/48599 , H01L2224/48699 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2224/83 , H01L2224/85 , H01L2225/06506 , H01L2225/0651 , H01L2225/06572 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： Disclosed is a semiconductor device packaging technique that is capable of resolving a problem of instability of bonding wires when stacking a plurality of semiconductor chips. The technique is also capable of realizing a slim, light and small package. The semiconductor device package includes a substrate having a substrate pad on a surface thereof, one or more memory chips stacked on the substrate with each memory chip having a pad connected to a common pin receiving a common signal applied to all the memory chips, an interposer chip stacked on the substrate and having an interconnection wire connected to the memory chip pad, the common pin of each of the memory chips being electrically connected to the interconnection wire via the memory chip pad, and a logic chip stacked on the substrate and having a bypass circuit which electrically connects or disconnects the interconnection wire to or from the substrate pad.
摘要翻译：公开了一种半导体器件封装技术，其能够在堆叠多个半导体芯片时解决接合线不稳定的问题。该技术还能够实现纤细，轻巧和小包装。半导体器件封装包括其表面上具有衬底焊盘的衬底，堆叠在衬底上的一个或多个存储器芯片，每个存储器芯片具有连接到接收施加到所有存储器芯片的公共信号的公共引脚的焊盘，插入器芯片堆叠在基板上并具有连接到存储器芯片焊盘的互连线，每个存储器芯片的公共引脚经由存储器芯片焊盘电连接到互连线，以及堆叠在基板上的逻辑芯片，旁路电路，其将互连线电连接到基板焊盘或从基板焊盘断开。

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