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1. 发明申请

US20120105264A1 ANALOG-TO-DIGITAL CONVERTER 有权
标题翻译：模拟数字转换器
公开(公告)号：US20120105264A1
公开(公告)日：2012-05-03
申请号：US12981664
申请日：2010-12-30
申请人： Seung-Tak Ryu , Jong-In Kim , Ki-Jin Kim , Kwang Ho Ahn
发明人： Seung-Tak Ryu , Jong-In Kim , Ki-Jin Kim , Kwang Ho Ahn
IPC分类号： H03M1/38
CPC分类号： H03M1/002 , H03M1/205 , H03M1/206 , H03M1/365
摘要： An analog-to-digital converter includes: a first latch row corresponding to a first stage; a second latch row corresponding to a second stage; and a digital processor for encoding output signals of the second latch row and generating a digital signal. The first latch row includes a plurality of first latches that receive an analog input signal and reference voltages and operate in synchronization with a first clock signal, and the second latch row includes: a plurality of second latches that receive outputs signals of the plurality of first latches and operate in synchronization with a second clock signal delayed from the first reference clock; and a plurality of third latches that receive output signals of two neighboring latches of the plurality of first latches and operate in synchronization with the second clock signal by means of an interpolation technique.
摘要翻译：模数转换器包括：对应于第一级的第一锁存行; 对应于第二级的第二锁存行; 以及用于对第二锁存行的输出信号进行编码并产生数字信号的数字处理器。第一锁存行包括接收模拟输入信号和参考电压并与第一时钟信号同步操作的多个第一锁存器，并且第二锁存行包括：多个第二锁存器，其接收多个第一锁存器的输出信号锁存并与从第一参考时钟延迟的第二时钟信号同步操作; 以及多个第三锁存器，其接收所述多个第一锁存器中的两个相邻锁存器的输出信号，并且通过插值技术与所述第二时钟信号同步地操作。

2. 发明授权

US08421664B2 Analog-to-digital converter 有权
标题翻译：模数转换器
公开(公告)号：US08421664B2
公开(公告)日：2013-04-16
申请号：US12981664
申请日：2010-12-30
申请人： Seung-Tak Ryu , Jong-In Kim , Ki-Jin Kim , Kwang Ho Ahn
发明人： Seung-Tak Ryu , Jong-In Kim , Ki-Jin Kim , Kwang Ho Ahn
IPC分类号： H03M1/12
CPC分类号： H03M1/002 , H03M1/205 , H03M1/206 , H03M1/365
摘要： An analog-to-digital converter includes: a first latch row corresponding to a first stage; a second latch row corresponding to a second stage; and a digital processor for encoding output signals of the second latch row and generating a digital signal. The first latch row includes a plurality of first latches that receive an analog input signal and reference voltages and operate in synchronization with a first clock signal, and the second latch row includes: a plurality of second latches that receive outputs signals of the plurality of first latches and operate in synchronization with a second clock signal delayed from the first reference clock; and a plurality of third latches that receive output signals of two neighboring latches of the plurality of first latches and operate in synchronization with the second clock signal by means of an interpolation technique.
摘要翻译：模数转换器包括：对应于第一级的第一锁存行; 对应于第二级的第二锁存行; 以及用于对第二锁存行的输出信号进行编码并产生数字信号的数字处理器。第一锁存行包括接收模拟输入信号和参考电压并与第一时钟信号同步操作的多个第一锁存器，并且第二锁存行包括：多个第二锁存器，其接收多个第一锁存器的输出信号锁存并与从第一参考时钟延迟的第二时钟信号同步操作; 以及多个第三锁存器，其接收所述多个第一锁存器中的两个相邻锁存器的输出信号，并且通过插值技术与所述第二时钟信号同步地操作。

3. 发明授权

US08874064B2 Ultrahigh frequency I/Q sender/receiver using multi-stage harmonic mixer 有权
标题翻译：使用多级谐波混频器的超高频I / Q发送器/接收器
公开(公告)号：US08874064B2
公开(公告)日：2014-10-28
申请号：US13325722
申请日：2011-12-14
申请人： Ki Jin Kim , Kwang Ho Ahn , Sanghoon Park
发明人： Ki Jin Kim , Kwang Ho Ahn , Sanghoon Park
IPC分类号： H04B15/00 , H03D7/16
CPC分类号： H03D7/163 , H03D7/165
摘要： A receiver using a harmonic mixer includes a signal receiver for receiving a first signal, a frequency generator for synchronizing a phase of the received first signal, down-converting a frequency size of the synchronized first signal as much as a first size, and outputting the down-converted signal as a second signal; a first harmonic mixer unit for receiving the first signal and the second signal, generating a third signal having a frequency size down-converted as much as a second size, and outputting the third signal. The receiver further includes a second harmonic mixer unit for receiving the third signal and outputting an In-phase signal having a frequency size down-converted as much as a third size, and a third harmonic mixer unit for receiving the third signal and outputting a Quadrature-phase signal having a frequency size down-converted as much as a third size.
摘要翻译：使用谐波混频器的接收机包括用于接收第一信号的信号接收器，用于使接收到的第一信号的相位同步的频率发生器，将同步的第一信号的频率大小向下转换为第一大小，并输出下变频信号作为第二信号; 用于接收第一信号和第二信号的第一谐波混频器单元，产生具有下变频倍数大小为第二大小的频率大小的第三信号，并输出第三信号。接收机还包括二次谐波混频器单元，用于接收第三信号并输出具有下变频多达第三大小的频率尺寸的同相信号;以及三次谐波混频器单元，用于接收第三信号并输出正交信号相位信号具有下变频多达第三尺寸的频率尺寸。

4. 发明申请

US20120162009A1 BEAMFORMING ARRAY ANTENNA CONTROL SYSTEM AND METHOD FOR BEAMFORMING USING THE SAME 有权
标题翻译：射束阵列天线控制系统及其使用方法
公开(公告)号：US20120162009A1
公开(公告)日：2012-06-28
申请号：US13325591
申请日：2011-12-14
申请人： Ki Jin Kim , Kwang Ho Ahn , Sanghoon Park , Jong-Won Yu , Hyun Sung Tae
发明人： Ki Jin Kim , Kwang Ho Ahn , Sanghoon Park , Jong-Won Yu , Hyun Sung Tae
IPC分类号： H01Q3/00
CPC分类号： H01Q25/00 , H01Q3/00
摘要： A control system connected to a plurality of array antenna performs beamforming. In order to perform the beamforming, the control system receives response beams inputting to a first antenna group predetermined from a plurality of array antenna in response to radiate beams and decides a sector having comparatively stronger intensity. And the control system receives response beams inputting to a second antenna group, decides a plurality of beam levels and decides a final beam pair among the plurality of the decided beam levels.
摘要翻译：连接到多个阵列天线的控制系统执行波束形成。为了执行波束形成，控制系统接收响应于辐射波束从多个阵列天线预定的第一天线组输入的响应波束，并且确定具有相对较强强度的扇区。并且控制系统接收输入到第二天线组的响应波束，决定多个波束级，并且决定多个所决定的波束级之间的最终波束对。

5. 发明授权

US09000981B2 Beamforming array antenna control system and method for beamforming using the same 有权
标题翻译：波束成形阵列天线控制系统及其波束成形方法
公开(公告)号：US09000981B2
公开(公告)日：2015-04-07
申请号：US13325591
申请日：2011-12-14
申请人： Ki Jin Kim , Kwang Ho Ahn , Sanghoon Park , Jong-Won Yu , Hyun Sung Tae
发明人： Ki Jin Kim , Kwang Ho Ahn , Sanghoon Park , Jong-Won Yu , Hyun Sung Tae
IPC分类号： H01Q3/12 , H01Q3/00 , H01Q25/00
CPC分类号： H01Q25/00 , H01Q3/00
摘要： A control system connected to a plurality of array antenna performs beamforming. In order to perform the beamforming, the control system receives response beams inputting to a first antenna group predetermined from a plurality of array antenna in response to radiate beams and decides a sector having comparatively stronger intensity. And the control system receives response beams inputting to a second antenna group, decides a plurality of beam levels and decides a final beam pair among the plurality of the decided beam levels.
摘要翻译：连接到多个阵列天线的控制系统执行波束形成。为了执行波束形成，控制系统接收响应于辐射波束从多个阵列天线预定的第一天线组输入的响应波束，并且确定具有相对较强强度的扇区。并且控制系统接收输入到第二天线组的响应波束，决定多个波束级，并且决定多个所决定的波束级之间的最终波束对。

6. 发明授权

US08373469B2 Phase-locked loop based frequency synthesizer and method of operating the same 有权
标题翻译：基于锁相环的频率合成器及其操作方法
公开(公告)号：US08373469B2
公开(公告)日：2013-02-12
申请号：US12981619
申请日：2010-12-30
申请人： Ki-Jin Kim , Kwang Ho Ahn
发明人： Ki-Jin Kim , Kwang Ho Ahn
IPC分类号： H03L7/06
CPC分类号： H03L7/1976 , H03L7/081 , H03L7/0816 , H03L7/087 , H03L7/1075 , H03L7/193 , H03L7/23
摘要： A phase-locked loop based frequency synthesizer generates a plurality of output reference signals by phase-delaying an input reference signal and generates a plurality of comparison signals by using a signal having a frequency divided by the fractional frequency divider. Here, the comparison signals are lower than the divided frequency. Further, the phase-locked loop based frequency synthesizer controls an output frequency of a voltage controlled oscillator through phase and frequency comparison between the plurality of output reference signals and the plurality of comparison signals.
摘要翻译：基于锁相环的频率合成器通过对输入参考信号进行相位延迟来产生多个输出参考信号，并通过使用具有由分数分频器分频的频率的信号来产生多个比较信号。这里，比较信号低于分频。此外，基于锁相环的频率合成器通过多个输出参考信号和多个比较信号之间的相位和频率比较来控制压控振荡器的输出频率。

7. 发明申请

US20120163493A1 ULTRAHIGH FREQUENCY I/Q SENDER/RECEIVER USING MULTI-STAGE HARMONIC MIXER 有权
标题翻译： ULTRAHIGH频率I / Q发送器/接收器使用多级谐波混频器
公开(公告)号：US20120163493A1
公开(公告)日：2012-06-28
申请号：US13325722
申请日：2011-12-14
申请人： Ki Jin Kim , Kwang Ho Ahn , Sanghoon Park
发明人： Ki Jin Kim , Kwang Ho Ahn , Sanghoon Park
IPC分类号： H04L27/00 , H04L27/06
CPC分类号： H03D7/163 , H03D7/165
摘要： A receiver using a harmonic mixer includes a signal receiver for receiving a first signal, a frequency generator for synchronizing a phase of the received first signal, down-converting a frequency size of the synchronized first signal as much as a first size, and outputting the down-converted signal as a second signal; a first harmonic mixer unit for receiving the first signal and the second signal, generating a third signal having a frequency size down-converted as much as a second size, and outputting the third signal. The receiver further includes a second harmonic mixer unit for receiving the third signal and outputting an In-phase signal having a frequency size down-converted as much as a third size, and a third harmonic mixer unit for receiving the third signal and outputting a Quadrature-phase signal having a frequency size down-converted as much as a third size.
摘要翻译：使用谐波混频器的接收机包括用于接收第一信号的信号接收器，用于使接收的第一信号的相位同步的频率发生器，将同步的第一信号的频率大小向下转换为第一大小，并输出下变频信号作为第二信号; 用于接收第一信号和第二信号的第一谐波混频器单元，产生具有下变频倍数大小为第二大小的频率大小的第三信号，并输出第三信号。接收机还包括二次谐波混频器单元，用于接收第三信号并输出具有下变频多达第三大小的频率尺寸的同相信号;以及三次谐波混频器单元，用于接收第三信号并输出正交信号相位信号具有下变频多达第三尺寸的频率尺寸。

8. 发明申请

US20120074997A1 PHASE-LOCKED LOOP BASED FREQUENCY SYNTHESIZER AND METHOD OF OPERATING THE SAME 有权
标题翻译：基于相位锁相环的频率合成器及其操作方法
公开(公告)号：US20120074997A1
公开(公告)日：2012-03-29
申请号：US12981619
申请日：2010-12-30
申请人： Ki-Jin Kim , Kwang Ho Ahn
发明人： Ki-Jin Kim , Kwang Ho Ahn
IPC分类号： H03L7/08
CPC分类号： H03L7/1976 , H03L7/081 , H03L7/0816 , H03L7/087 , H03L7/1075 , H03L7/193 , H03L7/23
摘要： A phase-locked loop based frequency synthesizer generates a plurality of output reference signals by phase-delaying an input reference signal and generates a plurality of comparison signals by using a signal having a frequency divided by the fractional frequency divider. Here, the comparison signals are lower than the divided frequency. Further, the phase-locked loop based frequency synthesizer controls an output frequency of a voltage controlled oscillator through phase and frequency comparison between the plurality of output reference signals and the plurality of comparison signals.
摘要翻译：基于锁相环的频率合成器通过对输入参考信号进行相位延迟来产生多个输出参考信号，并通过使用具有由分数分频器分频的频率的信号来产生多个比较信号。这里，比较信号低于分频。此外，基于锁相环的频率合成器通过多个输出参考信号和多个比较信号之间的相位和频率比较来控制压控振荡器的输出频率。

9. 发明申请

US20080199147A1 Apparatus for reproducing moving image stream with speed change and method thereof 审中-公开
标题翻译：用于再现速度变化的运动图像流的装置及其方法
公开(公告)号：US20080199147A1
公开(公告)日：2008-08-21
申请号：US12028642
申请日：2008-02-08
申请人： Young Ki Kim , Kwang Ho Ahn , Kyung Pa Min
发明人： Young Ki Kim , Kwang Ho Ahn , Kyung Pa Min
IPC分类号： H04N5/91
CPC分类号： G11B27/005 , G11B2220/20 , H04N5/781 , H04N5/783 , H04N9/8042 , H04N9/8047 , H04N9/8227
摘要： An apparatus and method for reproducing moving image stream with speed change, are discussed. According to an embodiment, the apparatus includes a receiving unit configured to receive a compressed moving image stream, a reconstruction unit configured to reconstruct an image from the compressed moving image stream, a generation unit configured to generate a still image from the reconstructed image, a recording unit configured to record the generated still image and a reproduction unit configured to perform a trick mode using the still image.
摘要翻译：讨论了用于再现具有速度变化的运动图像流的装置和方法。根据实施例，该装置包括：接收单元，被配置为接收压缩的运动图像流;重建单元，被配置为从压缩的运动图像流重建图像;生成单元，被配置为从重构图像生成静止图像; 被配置为记录所生成的静止图像的记录单元和被配置为使用静止图像执行特技模式的再现单元。

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