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1. 发明申请

US20160148888A1 SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING THE SAME 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20160148888A1
公开(公告)日：2016-05-26
申请号：US14948228
申请日：2015-11-20
申请人： Seung-Kwan RYU , Jongbo SHIM , Eunchul AHN , Taeje CHO
发明人： Seung-Kwan RYU , Jongbo SHIM , Eunchul AHN , Taeje CHO
IPC分类号： H01L23/00 , H01L23/48
CPC分类号： H01L24/14 , H01L23/3171 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L2224/0346 , H01L2224/0347 , H01L2224/0361 , H01L2224/03912 , H01L2224/0401 , H01L2224/05022 , H01L2224/05553 , H01L2224/05555 , H01L2224/05568 , H01L2224/05572 , H01L2224/0603 , H01L2224/06051 , H01L2224/06102 , H01L2224/06517 , H01L2224/09519 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/13007 , H01L2224/13012 , H01L2224/13017 , H01L2224/13021 , H01L2224/13023 , H01L2224/1308 , H01L2224/13147 , H01L2224/13155 , H01L2224/14051 , H01L2224/14104 , H01L2224/16238 , H01L2224/17517 , H01L2224/17519 , H01L2224/73204 , H01L2224/81191 , H01L2224/81203 , H01L2224/81444 , H01L2924/00012 , H01L2924/00014 , H01L2924/014
摘要： A semiconductor device may include a semiconductor substrate, a conductive pad on the semiconductor substrate, a passivation layer overlying the semiconductor substrate and exposing the conductive pad, and a bump structure. The bump structure may include a first bump structure on the conductive pad and a second bump structure on the passivation layer. The first bump structure may include a base bump layer, a first pillar bump layer, and a first solder bump layer that are sequentially stacked on the conductive pad. The second bump structure may include a second pillar bump layer and a second solder bump layer that are sequentially stacked on the passivation layer.
摘要翻译：半导体器件可以包括半导体衬底，半导体衬底上的导电焊盘，覆盖半导体衬底并暴露导电焊盘的钝化层和凸块结构。凸块结构可以包括导电焊盘上的第一凸起结构和钝化层上的第二凸起结构。第一凸块结构可以包括顺序地堆叠在导电焊盘上的基底凸起层，第一柱凸起层和第一焊料凸块层。第二凸起结构可以包括顺序地堆叠在钝化层上的第二柱状凸起层和第二焊料凸块层。

2. 发明申请

US20120280382A1 SEMICONDUCTOR PACKAGES 有权
标题翻译：半导体封装
公开(公告)号：US20120280382A1
公开(公告)日：2012-11-08
申请号：US13461949
申请日：2012-05-02
申请人： Yunhyeok IM , Kyol PARK , Taeje CHO
发明人： Yunhyeok IM , Kyol PARK , Taeje CHO
IPC分类号： H01L23/373
CPC分类号： H01L23/36 , H01L23/3128 , H01L23/427 , H01L23/4275 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/00
摘要： Semiconductor package are provided. In one embodiment, the semiconductor package may include a substrate such as a circuit substrate, a semiconductor chip mounted on the circuit substrate, a molding (or an encapsulant) covering the semiconductor chip and the circuit substrate and including a first temperature control member, and a heat dissipation member covering the molding.
摘要翻译：提供半导体封装。在一个实施例中，半导体封装可以包括诸如电路基板的基板，安装在电路基板上的半导体芯片，覆盖半导体芯片和电路基板并包括第一温度控制构件的模制件（或密封剂），以及覆盖模制件的散热构件。

3. 发明申请

US20160079208A1 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US20160079208A1
公开(公告)日：2016-03-17
申请号：US14821767
申请日：2015-08-09
申请人： Junyeong HEO , CHAJEA JO , Taeje CHO
发明人： Junyeong HEO , CHAJEA JO , Taeje CHO
IPC分类号： H01L25/065 , H01L23/48 , H01L23/00
CPC分类号： H01L25/0657 , H01L23/3677 , H01L23/481 , H01L23/49827 , H01L23/544 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/33 , H01L24/81 , H01L24/83 , H01L24/92 , H01L24/94 , H01L25/50 , H01L2223/5442 , H01L2223/54426 , H01L2223/5448 , H01L2224/0361 , H01L2224/0401 , H01L2224/0557 , H01L2224/05624 , H01L2224/05647 , H01L2224/05655 , H01L2224/06181 , H01L2224/1403 , H01L2224/14131 , H01L2224/14136 , H01L2224/14177 , H01L2224/14179 , H01L2224/14505 , H01L2224/14519 , H01L2224/16145 , H01L2224/16227 , H01L2224/1703 , H01L2224/17051 , H01L2224/17177 , H01L2224/17181 , H01L2224/2919 , H01L2224/32145 , H01L2224/32148 , H01L2224/32225 , H01L2224/33181 , H01L2224/73204 , H01L2224/73253 , H01L2224/8113 , H01L2224/83104 , H01L2224/92125 , H01L2224/94 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06565 , H01L2225/06589 , H01L2225/06593 , H01L2924/15311 , H01L2924/3512 , H01L2224/03 , H01L2924/00 , H01L2924/00014 , H01L2224/17136 , H01L2224/17179
摘要： An embodiment includes a semiconductor package comprising: a substrate; a first semiconductor chip mounted on the substrate; a second semiconductor chip mounted on a top surface of the first semiconductor chip; a connecting bump disposed between the first and second semiconductor chips to electrically connect the second semiconductor chip to the first semiconductor chip; and a first heat dissipation part disposed on the top surface of the first semiconductor chip between the first and second semiconductor chips and spaced apart from a bottom surface of the second semiconductor chip.
摘要翻译：一个实施例包括半导体封装，包括：衬底; 安装在所述基板上的第一半导体芯片; 安装在所述第一半导体芯片的顶表面上的第二半导体芯片; 设置在所述第一和第二半导体芯片之间以将所述第二半导体芯片电连接到所述第一半导体芯片的连接凸块; 以及第一散热部，其设置在第一和第二半导体芯片之间的第一半导体芯片的顶表面上并且与第二半导体芯片的底表面间隔开。

4. 发明申请

US20150171028A1 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：半导体封装及其制造方法
公开(公告)号：US20150171028A1
公开(公告)日：2015-06-18
申请号：US14492556
申请日：2014-09-22
申请人： CHAJEA JO , Taeje CHO , YUNHYEOK IM
发明人： CHAJEA JO , Taeje CHO , YUNHYEOK IM
IPC分类号： H01L23/00 , H01L21/78 , H01L21/56 , H01L21/52 , H01L23/31 , H01L23/36
CPC分类号： H01L23/562 , H01L21/78 , H01L23/3128 , H01L23/36 , H01L23/481 , H01L23/49816 , H01L23/49822 , H01L25/0657 , H01L25/105 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06586 , H01L2225/06589 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2225/1094 , H01L2924/15311 , H01L2924/1815 , H01L2924/18161 , H01L2924/3511 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor package is provided. At least one semiconductor chip is mounted on a package substrate. A mold layer covers the at least one semiconductor chip. The mold layer exposes a portion of a top surface of an uppermost semiconductor chip of the at least one semiconductor chip.
摘要翻译：提供半导体封装。至少一个半导体芯片安装在封装衬底上。模具层覆盖至少一个半导体芯片。模层暴露至少一个半导体芯片的最上半导体芯片的顶表面的一部分。

5. 发明申请

US20150123284A1 SEMICONDUCTOR DEVICES HAVING THROUGH-ELECTRODES AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：具有电极的半导体器件及其制造方法
公开(公告)号：US20150123284A1
公开(公告)日：2015-05-07
申请号：US14470366
申请日：2014-08-27
申请人： Chajea JO , Taeje CHO , Hyunsoo CHUNG
发明人： Chajea JO , Taeje CHO , Hyunsoo CHUNG
IPC分类号： H01L23/538 , H01L25/065 , H01L21/768
CPC分类号： H01L23/5384 , H01L21/76879 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L2224/16145 , H01L2224/16225 , H01L2924/15311
摘要： A semiconductor device having through-electrodes and methods for fabricating the same are provided. The semiconductor device may include a first semiconductor chip including a first active surface on which a first top pad is provided; a second semiconductor chip including a second active surface on which a second top pad is provided and a second inactive surface on which a second bottom pad is provided, the second semiconductor chip being stacked on the first semiconductor chip with the second active surface facing the first active surface; and a conductive interconnection configured to electrically connect the chips. The conductive interconnection includes a first through-electrode that penetrates the second semiconductor chip and electrically connects the second bottom pad to the second top pad; and a second through-electrode that passes through the second top pad without contacting the second top pad, and electrically connects the second bottom pad to the first top pad.
摘要翻译：提供了具有贯通电极的半导体器件及其制造方法。半导体器件可以包括第一半导体芯片，其包括第一有源表面，第一有源表面上设置有第一顶部焊盘; 包括第二有源表面的第二半导体芯片，其上设置有第二顶焊盘，第二非活性表面设置有第二底焊盘，第二半导体芯片堆叠在第一半导体芯片上，第二有源表面面向第一活性表面以及被配置为电连接芯片的导电互连。导电互连包括穿透第二半导体芯片并将第二底部焊盘电连接到第二顶部焊盘的第一贯通电极; 以及第二贯通电极，其穿过所述第二顶部焊盘而不接触所述第二顶部焊盘，并且将所述第二底部焊盘电连接到所述第一顶部焊盘。

6. 发明申请

US20160133613A1 SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE HAVING HEAT DISSIPATION 审中-公开
标题翻译：具有散热功能的半导体封装和电子器件
公开(公告)号：US20160133613A1
公开(公告)日：2016-05-12
申请号：US14841736
申请日：2015-09-01
申请人： SUNKYOUNG SEO , CHAJEA JO , JI HWANG KIM , Taeje CHO
发明人： SUNKYOUNG SEO , CHAJEA JO , JI HWANG KIM , Taeje CHO
IPC分类号： H01L25/10 , H01L23/367 , H01L23/31
CPC分类号： H01L25/105 , H01L23/13 , H01L23/3128 , H01L23/36 , H01L23/3677 , H01L23/481 , H01L23/49816 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/17 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/18 , H01L2224/0401 , H01L2224/04042 , H01L2224/0557 , H01L2224/13025 , H01L2224/131 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/14181 , H01L2224/14519 , H01L2224/16225 , H01L2224/16227 , H01L2224/16235 , H01L2224/17181 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/06568 , H01L2225/1023 , H01L2225/1058 , H01L2225/1076 , H01L2225/1094 , H01L2924/00014 , H01L2924/1431 , H01L2924/1434 , H01L2924/15159 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18161 , H01L2924/00012 , H01L2924/014 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2924/00
摘要： A semiconductor package is provided. The semiconductor package include a lower semiconductor package including a lower package substrate and a lower semiconductor chip mounted thereon, and an upper semiconductor package provided on the lower semiconductor package to include an upper package substrate and an upper semiconductor chip mounted thereon. The upper package substrate include an upper heat-dissipation pattern, the lower semiconductor chip include a first via connected to the upper heat-dissipation pattern through the lower semiconductor chip, and the first via may provide a pathway for dissipating heat generated in the lower semiconductor chip.
摘要翻译：提供半导体封装。半导体封装包括下半导体封装，其包括下封装衬底和安装在其上的下半导体芯片，以及设置在下半导体封装上的上半导体封装，以包括安装在其上的上封装衬底和上半导体芯片。上封装衬底包括上部散热图案，下半导体芯片包括通过下半导体芯片连接到上部散热图案的第一通孔，并且第一通孔可以提供用于耗散在下半导体中产生的热的路径芯片。

7. 发明申请

US20150380394A1 SEMICONDUCTOR PACKAGES AND METHODS FOR FABRICATING THE SAME 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US20150380394A1
公开(公告)日：2015-12-31
申请号：US14744031
申请日：2015-06-19
申请人： Hye-young JANG , Chang-Seong JEON , CHAJEA JO , Taeje CHO
发明人： Hye-young JANG , Chang-Seong JEON , CHAJEA JO , Taeje CHO
IPC分类号： H01L25/00 , H01L21/56 , H01L23/00 , H01L25/065 , H01L25/18
CPC分类号： H01L25/0657 , H01L23/3128 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/17 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/83 , H01L24/92 , H01L25/18 , H01L25/50 , H01L2224/02372 , H01L2224/0401 , H01L2224/05568 , H01L2224/05569 , H01L2224/0557 , H01L2224/06181 , H01L2224/131 , H01L2224/1412 , H01L2224/1413 , H01L2224/16146 , H01L2224/16227 , H01L2224/17104 , H01L2224/2919 , H01L2224/32013 , H01L2224/321 , H01L2224/32145 , H01L2224/33181 , H01L2224/73104 , H01L2224/73204 , H01L2224/81191 , H01L2224/81203 , H01L2224/83191 , H01L2224/83203 , H01L2224/83379 , H01L2224/92 , H01L2224/9211 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06544 , H01L2225/06555 , H01L2225/06582 , H01L2225/06589 , H01L2924/1434 , H01L2924/15311 , H01L2924/18161 , H01L2924/181 , H01L2924/00012 , H01L2924/014
摘要： A semiconductor package may include a first semiconductor chip including a first surface facing a package substrate, a second surface opposite to the first surface, and at least one through-electrode penetrating the first semiconductor chip, a molding layer molding the first semiconductor chip and exposing the second surface of the first semiconductor chip, a second semiconductor chip stacked on the second surface of the first semiconductor chip, and a non-conductive film provided between the first and second semiconductor chips. The second semiconductor chip includes an overhang portion extending past an edge of the first semiconductor chip. For example, a size of the second semiconductor chip may be greater than that of the first semiconductor chip, so the second semiconductor chip has an overhang. The second semiconductor chip includes at least one interconnecting terminal electrically connected to the at least one through-electrode.
摘要翻译：半导体封装可以包括第一半导体芯片，其包括面向封装基板的第一表面，与第一表面相对的第二表面，以及穿透第一半导体芯片的至少一个贯通电极，模制第一半导体芯片的模制层和暴露第一半导体芯片的第二表面，堆叠在第一半导体芯片的第二表面上的第二半导体芯片，以及设置在第一和第二半导体芯片之间的非导电膜。第二半导体芯片包括延伸穿过第一半导体芯片的边缘的突出部分。例如，第二半导体芯片的尺寸可以大于第一半导体芯片的尺寸，因此第二半导体芯片具有突出端。第二半导体芯片包括电连接到至少一个通孔的至少一个互连端子。

8. 发明申请

US20160013174A1 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US20160013174A1
公开(公告)日：2016-01-14
申请号：US14736247
申请日：2015-06-10
申请人： Sang-Uk HAN , Seungwon PARK , Un-Byoung KANG , Taeje CHO
发明人： Sang-Uk HAN , Seungwon PARK , Un-Byoung KANG , Taeje CHO
IPC分类号： H01L25/00 , H01L21/82 , H01L23/48 , H01L21/56
CPC分类号： H01L25/50 , H01L21/561 , H01L21/568 , H01L21/82 , H01L23/3128 , H01L2224/16145 , H01L2224/32145 , H01L2224/73204 , H01L2224/97 , H01L2924/15311 , H01L2924/00
摘要： Embodiments of the inventive concepts provide a semiconductor package and a method of fabricating the same. The method includes forming a groove to separate first semiconductor chips from each other. Forming the groove include performing a first sawing process on a bottom surface of a semiconductor substrate to cut the semiconductor substrate and a portion of a mold layer in a direction inclined with respect to the bottom surface, and performing a second sawing process to cut the mold layer in a direction substantially perpendicular to the bottom surface of the semiconductor substrate. A minimum width of the groove formed in the semiconductor substrate by the first sawing process may be greater than a width of the groove formed in the mold layer by the second sawing process.
摘要翻译：本发明构思的实施例提供一种半导体封装及其制造方法。该方法包括形成沟槽以将第一半导体芯片彼此分开。形成凹槽包括在半导体衬底的底表面上执行第一锯切工艺以在相对于底表面倾斜的方向上切割半导体衬底和模具层的一部分，并且执行第二锯切工艺以切割模具层在基本上垂直于半导体衬底的底表面的方向上。通过第一锯切工艺在半导体衬底中形成的槽的最小宽度可以大于通过第二锯切工艺在模具层中形成的槽的宽度。

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