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1. 发明申请

US20060168156A1 Hierarchical system configuration method and integrated scheduling method to provide multimedia streaming service on two-level double cluster system 有权
公开(公告)号：US20060168156A1
公开(公告)日：2006-07-27
申请号：US11290073
申请日：2005-11-30
申请人： Seung Bae , Jin Kim , Seung Jeon , Hag Kim , Myung Kim
发明人： Seung Bae , Jin Kim , Seung Jeon , Hag Kim , Myung Kim
IPC分类号： G06F15/177
CPC分类号： H04L67/1008 , H04L67/1002 , Y10S707/99939
摘要： A hierarchical system configuration method and an integrated scheduling method for offering a multimedia streaming service on a two-level double cluster system are provided. The hierarchical system configuration method includes the steps of: determining whether one server node exists; if one server node exists, determining whether one virtual server node/specific network storing and merging block exists; and if one virtual server node/specific network storing and merging block exists, setting a system configuration mode for configuring a single virtual server node based multimedia streaming server system and determining a representative network address of a current system, wherein depending on a scale and a characteristic of the multimedia streaming service, a hierarchical multimedia streaming server system is configured into a single virtual server node based system, which is a minimum-scale, a mono-level single virtual cluster based system, which is a medium-scale, and a two-level double cluster based system, which is a maximum-scale.

2. 发明申请

US20060136487A1 Clustering apparatus and method for content delivery system by content classification 审中-公开
标题翻译：内容分类系统的聚类设备和方法
公开(公告)号：US20060136487A1
公开(公告)日：2006-06-22
申请号：US11300968
申请日：2005-12-15
申请人： Jin Kim , Seung Bae , Sang Woo , Yuhyeon Bak , Hag Kim , Myung Kim
发明人： Jin Kim , Seung Bae , Sang Woo , Yuhyeon Bak , Hag Kim , Myung Kim
IPC分类号： G06F17/00
CPC分类号： H04L67/06 , H04L67/1095 , H04L67/1097
摘要： A clustering apparatus and method for content delivery system are provided. The clustering apparatus includes: a local server for performing operations as a dedicated server providing a stream service by being connected to a cluster; and a file management server for storing original contents.
摘要翻译：提供了一种用于内容传送系统的聚类设备和方法。集群装置包括：本地服务器，用于通过连接到集群来执行作为提供流服务的专用服务器的操作; 以及用于存储原始内容的文件管理服务器。

3. 发明申请

US20070136314A1 Contents providing system and method for preventing improper contents purging and method for managing contents 审中-公开
标题翻译：内容提供用于防止不正当内容清除的系统和方法以及管理内容的方法
公开(公告)号：US20070136314A1
公开(公告)日：2007-06-14
申请号：US11633829
申请日：2006-12-05
申请人： Seung Bae , Jin Kim , Young Woo , Myung Kim
发明人： Seung Bae , Jin Kim , Young Woo , Myung Kim
IPC分类号： G06F17/30
CPC分类号： H04L67/16 , H04L67/1095 , H04L67/327
摘要： Provided is a contents providing system. The system includes a storing unit, a plurality of server nodes, a dispatcher node, and a storing/deleting management node. The storing unit stores synchronization data according to a service state of each contents data that can be provided. The plurality of server nodes change synchronization data of contents, and provides the contents service in response to a contents service request input via a network. The dispatcher node checks a service state of contents to select a server node that is to provide the corresponding contents service, and changes synchronization data to transmit address data of the selected server node and a corresponding contents file data to a client that has requested the contents service. The storing/deleting management node manages storing and deleting of contents data stored in a contents storing unit with reference to the synchronization data stored in the storing unit.
摘要翻译：提供内容提供系统。该系统包括存储单元，多个服务器节点，调度器节点和存储/删除管理节点。存储单元根据可以提供的每个内容数据的服务状态来存储同步数据。多个服务器节点改变内容的同步数据，并响应于经由网络输入的内容服务请求提供内容服务。调度节点检查内容的服务状态，选择要提供相应的内容服务的服务器节点，并改变同步数据，将选定的服务器节点的地址数据和相应的内容文件数据发送给请求内容的客户端服务。存储/删除管理节点参照存储在存储单元中的同步数据来管理存储在内容存储单元中的内容数据的存储和删除。

4. 发明申请

US20050007168A1 Digital duty cycle correction circuit and method for multi-phase clock 失效
公开(公告)号：US20050007168A1
公开(公告)日：2005-01-13
申请号：US10774398
申请日：2004-02-10
申请人： Hong Park , Young Jang , Seung Bae
发明人： Hong Park , Young Jang , Seung Bae
IPC分类号： H03K5/00 , H03K3/017 , H03K5/156
CPC分类号： H03K5/1565
摘要： Provided is a digital duty cycle correction circuit and method for a multi-phase clock, in which duty cycle correction information of an input clock signal is stored in a power save state of a system by adopting a digital correction method in a duty cycle correction method for a multi-phase clock and phase information of the input clock signal is held constant during duty cycle correction of the input clock signal by correcting duty cycles of the input clock signal by changing the falling edge of the clock without changing the rising edge of the input clock signal during duty cycle correction of the input clock signal, thereby correcting the multi-phase clock. To this end, the digital duty cycle correction circuit includes a clock delay means that takes the form of a shunt capacitor-inverter, a clock generation means including a clock rising edge generation circuit and a clock falling edge generation circuit, and a digital duty cycle detection means including integrators, a comparator, and a counter/register.

5. 发明申请

US20060146627A1 Memory system having multi-terminated multi-drop bus 失效
标题翻译：具有多端口多点总线的存储系统
公开(公告)号：US20060146627A1
公开(公告)日：2006-07-06
申请号：US11142873
申请日：2005-06-01
申请人： Hong Park , Seung Bae
发明人： Hong Park , Seung Bae
IPC分类号： G11C7/00
CPC分类号： G11C7/1048 , G11C5/063
摘要： Provided is a memory system having a multi-drop bus structure. The memory system includes a bus, a memory controller in which a port connected to the bus is terminated by a resistor having a first impedance value, a connector connected to a point having the first impedance value from the memory controller on a bus line, and a memory module connected to the connector. The memory module includes a first load connected to the connector and having the first impedance value, a second load connected to the first load and having a second impedance value, a first chip in which a port connected to the second load is terminated by a resistor having the second impedance value, a via hole penetrating a printed circuit board of the memory module between the first load and the second load, a third load connected to the via hole and having the second impedance value, and a second chip in which a port connected to the third load is terminated by a resistor having the second impedance value. The first load, the second load, and a first chip are formed on a first surface of the memory module while the third load and the second chip are formed on a second surface thereof.
摘要翻译：提供了具有多点总线结构的存储器系统。存储器系统包括总线，存储器控制器，其中连接到总线的端口由具有第一阻抗值的电阻器端接，连接到总线上的来自存储器控制器的具有第一阻抗值的点的连接器，以及连接到连接器的存储器模块。存储器模块包括连接到连接器并具有第一阻抗值的第一负载，连接到第一负载的第二负载并具有第二阻抗值;第一芯片，其中连接到第二负载的端口由电阻器具有第二阻抗值，穿过第一负载和第二负载之间的存储器模块的印刷电路板的通孔，连接到通孔并具有第二阻抗值的第三负载，以及第二芯片，其中端口连接到第三负载的电阻由具有第二阻抗值的电阻器终止。第一负载，第二负载和第一芯片形成在存储模块的第一表面上，而第三负载和第二芯片形成在其第二表面上。

6. 发明申请

US20060145740A1 VCDL-based dual loop DLL having infinite phase shift function 失效
标题翻译：基于VCDL的双循环DLL具有无限相移功能
公开(公告)号：US20060145740A1
公开(公告)日：2006-07-06
申请号：US11142698
申请日：2005-06-01
申请人： Hong Park , Seung Bae
发明人： Hong Park , Seung Bae
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/0812 , H03L7/0814
摘要： Provided is a dual loop DLL for generating an internal clock signal synchronized with an external clock, which includes a reference DLL receiving a reference clock and generating a plurality of phase clock signals having a first phase difference, a coarse loop selecting one of the phase clock signals and generating first through third digital codes to allow the internal clock signal to have a phase difference smaller than a second phase difference with respect to the external clock, and a fine loop selecting two of the phase clock signals and synchronizing the internal clock signal with the external clock, in response to the first through third digital codes.
摘要翻译：提供了一种用于产生与外部时钟同步的内部时钟信号的双循环DLL，其包括接收参考时钟并产生具有第一相位差的多个相位时钟信号的参考DLL，粗略选择相位时钟之一信号并产生第一至第三数字代码，以允许内部时钟信号相对于外部时钟具有小于第二相位差的相位差，以及选择两个相位时钟信号并使内部时钟信号与外部时钟，响应于第一到第三数字代码。

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