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1. 发明授权

US09917581B2 Electronic device and method for operating a power switch 有权
公开(公告)号：US09917581B2
公开(公告)日：2018-03-13
申请号：US14398318
申请日：2012-05-29
申请人： Sergey Sofer , Eyal Melamed-Kohen , Michael Priel
发明人： Sergey Sofer , Eyal Melamed-Kohen , Michael Priel
IPC分类号： H03K17/30 , H03K17/94 , H03K17/0412 , H03K17/693
CPC分类号： H03K17/94 , H03K17/04123 , H03K17/302 , H03K17/693 , Y10T307/344 , Y10T307/549
摘要： An electronic device comprising a first power switch connectable or connected between a first voltage source and a load is proposed. The first power switch assumes a conductive state in response to a power-on request and a non-conductive state in response to a power-off request, for energizing and deenergizing the load, so that a voltage across the first power switch tends to a positive high level when the first power switch is in the non-conductive state and to a positive low level when the first power switch is in the conductive state. The device further comprises a second power switch connectable or connected between a second voltage source and the load. The second power switch assumes a conductive state in response to the power-on request and a non-conductive state when the voltage across the first power switch is below a defined switch-off threshold lower than the high level. The second voltage source thus assists the first voltage source in powering up the load. A method of operating the electronic device is also described.

2. 发明申请

US20150084417A1 ELECTRONIC DEVICE AND METHOD FOR OPERATING A POWER SWITCH 有权
标题翻译：电子设备和操作电源开关的方法
公开(公告)号：US20150084417A1
公开(公告)日：2015-03-26
申请号：US14398318
申请日：2012-05-29
申请人： Sergey Sofer , Eyal Melamed-Kohen , Michael Priel
发明人： Sergey Sofer , Eyal Melamed-Kohen , Michael Priel
IPC分类号： H03K17/94 , H03K17/30
CPC分类号： H03K17/94 , H03K17/04123 , H03K17/302 , H03K17/693 , Y10T307/344 , Y10T307/549
摘要： An electronic device comprising a first power switch connectable or connected between a first voltage source and a load is proposed. The first power switch assumes a conductive state in response to a power-on request and a non-conductive state in response to a power-off request, for energizing and deenergizing the load, so that a voltage across the first power switch tends to a positive high level when the first power switch is in the non-conductive state and to a positive low level when the first power switch is in the conductive state. The device further comprises a second power switch connectable or connected between a second voltage source and the load. The second power switch assumes a conductive state in response to the power-on request and a non-conductive state when the voltage across the first power switch is below a defined switch-off threshold lower than the high level. The second voltage source thus assists the first voltage source in powering up the load. A method of operating the electronic device is also described.
摘要翻译：提出了一种包括可连接或连接在第一电压源和负载之间的第一电源开关的电子设备。响应于断电请求，第一电源开关响应于上电请求和非导通状态而呈现导通状态，用于对负载进行供电和断电，使得第一电源开关上的电压趋向于当第一电源开关处于导通状态时，当第一电源开关处于非导通状态时为正高电平，并且在第一电源开关处于导通状态时为正高电平。该装置还包括可连接或连接在第二电压源和负载之间的第二电源开关。当第一功率开关上的电压低于低于高电平的限定的关断阈值时，第二电源开关响应于电源接通请求而呈现导通状态和非导通状态。因此，第二电压源因此辅助第一电压源来加载负载。还描述了操作电子设备的方法。

3. 发明申请

US20110291740A1 METHOD FOR SUPPLYING AN OUTPUT SUPPLY VOLTAGE TO A POWER GATED CIRCUIT AND AN INTEGRATED CIRCUIT 有权
标题翻译：向输入电源和集成电路供电输出电压的方法
公开(公告)号：US20110291740A1
公开(公告)日：2011-12-01
申请号：US12787457
申请日：2010-05-26
申请人： Sergey Sofer , Eyal Melamed-Kohen , Valery Neiman
发明人： Sergey Sofer , Eyal Melamed-Kohen , Valery Neiman
IPC分类号： H03K17/00
CPC分类号： H03K19/0016
摘要： An integrated circuit, that includes: (i) a power gating switch, the power gating switch includes (a) an input port for receiving an input supply voltage; (b) an output port for outputting an output supply voltage; and (c) a control port for receiving a control signal that determines a difference between a value of the input supply voltage and a value of the output supply voltage; (ii) a power gated circuit, coupled to the output port of the switch, for receiving the output supply voltage; (iii) a mode indicator generator for generating a mode indicator that indicates of a desired mode of the power gated circuit; (iv) a leakage indicator generator for generating a leakage indicator that indicates of a leakage level of the power gated circuit; and (iv) a control circuit, for receiving the mode indicator and the leakage indicator, and for selecting the value of the control signal based on the mode indicator and on the leakage indicator.
摘要翻译：一种集成电路，包括：（i）电源门控开关，电源门控开关包括（a）用于接收输入电源电压的输入端口; （b）用于输出输出电源电压的输出端口; 和（c）控制端口，用于接收确定输入电源电压值与输出电源电压值之间的差的控制信号; （ii）耦合到开关的输出端口的电源门控电路，用于接收输出电源电压; （iii）模式指示器发生器，用于产生指示电力门控电路的期望模式的模式指示器; （iv）泄漏指示器发生器，用于产生指示电力门控电路的泄漏电平的泄漏指示器; 以及（iv）控制电路，用于接收模式指示器和泄漏指示器，并且用于基于模式指示器和泄漏指示器来选择控制信号的值。

4. 发明申请

US20140077856A1 INTEGRATED CIRCUIT DEVICE AND METHOD FOR SELF-HEATING AN INTEGRATED CIRCUIT DEVICE 审中-公开
标题翻译：集成电路装置及自动加热集成电路装置的方法
公开(公告)号：US20140077856A1
公开(公告)日：2014-03-20
申请号：US14115710
申请日：2011-05-27
申请人： Sergey Sofer , Moty Groissman , Eyal Melamed-Kohen , Naom Sivam
发明人： Sergey Sofer , Moty Groissman , Eyal Melamed-Kohen , Naom Sivam
IPC分类号： H03K3/011
CPC分类号： H03K3/011 , G06F1/206 , H03K3/0375 , Y02D10/16
摘要： An integrated circuit device comprises a first clock signal source, arranged to provide at least one first clock signal; a second clock signal source, arranged to provide at least one second clock signal different from the at least one first clock signal; and a plurality of sequential logic cells, at least one of the plurality connected to receive, in a first mode, the at least one first clock signal or at least one clock signal derived from the at least one first clock signal, and to receive, in a second mode, the at least one second clock signal or at least one clock signal derived from the at least one second clock signal; wherein in the second mode the at least one second clock signal is adapted to the at least one of the plurality of sequential logic cells to generate in at least a portion of the integrated circuit device a current consumption when the at least one first clock signal is not a toggling signal.
摘要翻译：集成电路装置包括第一时钟信号源，被布置成提供至少一个第一时钟信号; 第二时钟信号源，被布置成提供与所述至少一个第一时钟信号不同的至少一个第二时钟信号; 以及多个顺序逻辑单元，所述多个顺序逻辑单元中的至少一个连接成以第一模式接收所述至少一个第一时钟信号或从所述至少一个第一时钟信号导出的至少一个时钟信号，在第二模式中，所述至少一个第二时钟信号或从所述至少一个第二时钟信号导出的至少一个时钟信号; 其中在所述第二模式中，所述至少一个第二时钟信号适用于所述多个顺序逻辑单元中的至少一个，以在所述至少一个第一时钟信号为不是切换信号。

5. 发明申请

US20120169391A1 DUTY CYCLE CORRECTOR AND DUTY CYCLE CORRECTION METHOD 有权
标题翻译：占空比校正和占空比校正方法
公开(公告)号：US20120169391A1
公开(公告)日：2012-07-05
申请号：US13392638
申请日：2009-09-24
申请人： Sergey Sofer , Eyal Melamed-Kohen , Valery Neiman
发明人： Sergey Sofer , Eyal Melamed-Kohen , Valery Neiman
IPC分类号： H03K5/04 , H03K3/017
CPC分类号： H03K5/1565
摘要： The invention relates to a duty cycle corrector for generating from an input clock signal an output clock signal having a desired duty cycle. The duty cycle corrector comprises a pulse generating stage for generating from the input clock signal a pulsed clock signal. The pulse generating stage converts rising edges of the input clock signal into pulses, each of which pulses is shorter than the desired duty cycle times the clock period. The duty cycle corrector further comprises a pulse stretching stage for generating from the pulsed clock signal the output clock signal, the pulse stretching stage delaying falling edges of the pulsed clock signal by a controlled delay. The duty cycle corrector may comprise a duty cycle detector for generating a control signal as a function of the duty cycle of the output clock signal, and a feedback path for delivering the control signal to the pulse stretching stage so as to increase the controlled delay when the duty cycle is less than the desired duty cycle and to decrease the controlled delay when the duty cycle is greater than the desired duty cycle. The invention also relates to a method of generating from an input clock signal an output clock signal having a desired duty cycle.
摘要翻译：本发明涉及一种占空比校正器，用于从输入时钟信号产生具有期望占空比的输出时钟信号。占空比校正器包括用于从输入时钟信号产生脉冲时钟信号的脉冲发生级。脉冲发生级将输入时钟信号的上升沿转换成脉冲，每个脉冲比期望的占空比短于时钟周期。占空比校正器还包括用于从脉冲时钟信号产生输出时钟信号的脉冲拉伸级，脉冲延伸级以受控的延迟延迟脉冲时钟信号的下降沿。占空比校正器可以包括用于产生作为输出时钟信号的占空比的函数的控制信号的占空比检测器，以及用于将控制信号传送到脉冲拉伸级的反馈路径，以便当占空比小于期望的占空比，并且当占空比大于期望的占空比时减小受控延迟。本发明还涉及一种从输入时钟信号产生具有期望占空比的输出时钟信号的方法。

6. 发明授权

US08081026B1 Method for supplying an output supply voltage to a power gated circuit and an integrated circuit 有权
标题翻译：用于向电源门控电路和集成电路提供输出电源电压的方法
公开(公告)号：US08081026B1
公开(公告)日：2011-12-20
申请号：US12787457
申请日：2010-05-26
申请人： Sergey Sofer , Eyal Melamed-Kohen , Valery Neiman
发明人： Sergey Sofer , Eyal Melamed-Kohen , Valery Neiman
IPC分类号： G05F1/10
CPC分类号： H03K19/0016
摘要： An integrated circuit, that includes: (i) a power gating switch, the power gating switch includes (a) an input port for receiving an input supply voltage; (b) an output port for outputting an output supply voltage; and (c) a control port for receiving a control signal that determines a difference between a value of the input supply voltage and a value of the output supply voltage; (ii) a power gated circuit, coupled to the output port of the switch, for receiving the output supply voltage; (iii) a mode indicator generator for generating a mode indicator that indicates of a desired mode of the power gated circuit; (iv) a leakage indicator generator for generating a leakage indicator that indicates of a leakage level of the power gated circuit; and (iv) a control circuit, for receiving the mode indicator and the leakage indicator, and for selecting the value of the control signal based on the mode indicator and on the leakage indicator.
摘要翻译：一种集成电路，包括：（i）电源门控开关，电源门控开关包括（a）用于接收输入电源电压的输入端口; （b）用于输出输出电源电压的输出端口; 和（c）控制端口，用于接收确定输入电源电压值与输出电源电压值之间的差的控制信号; （ii）耦合到开关的输出端口的电源门控电路，用于接收输出电源电压; （iii）模式指示器发生器，用于产生指示电力门控电路的期望模式的模式指示器; （iv）泄漏指示器发生器，用于产生指示电力门控电路的泄漏电平的泄漏指示器; 以及（iv）控制电路，用于接收模式指示器和泄漏指示器，并且用于基于模式指示器和泄漏指示器来选择控制信号的值。

7. 发明授权

US08552778B2 Duty cycle corrector and duty cycle correction method 有权
标题翻译：占空比校正器和占空比校正方法
公开(公告)号：US08552778B2
公开(公告)日：2013-10-08
申请号：US13392638
申请日：2009-09-24
申请人： Sergey Sofer , Eyal Melamed-Kohen , Valery Neiman
发明人： Sergey Sofer , Eyal Melamed-Kohen , Valery Neiman
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： The invention relates to a duty cycle corrector for generating from an input clock signal an output clock signal having a desired duty cycle. The duty cycle corrector comprises a pulse generating stage for generating from the input clock signal a pulsed clock signal. The pulse generating stage converts rising edges of the input clock signal into pulses, each of which pulses is shorter than the desired duty cycle times the clock period. The duty cycle corrector further comprises a pulse stretching stage for generating from the pulsed clock signal the output clock signal, the pulse stretching stage delaying falling edges of the pulsed clock signal by a controlled delay. The duty cycle corrector may comprise a duty cycle detector for generating a control signal as a function of the duty cycle of the output clock signal, and a feedback path for delivering the control signal to the pulse stretching stage so as to increase the controlled delay when the duty cycle is less than the desired duty cycle and to decrease the controlled delay when the duty cycle is greater than the desired duty cycle. The invention also relates to a method of generating from an input clock signal an output clock signal having a desired duty cycle.
摘要翻译：本发明涉及一种占空比校正器，用于从输入时钟信号产生具有期望占空比的输出时钟信号。占空比校正器包括用于从输入时钟信号产生脉冲时钟信号的脉冲发生级。脉冲发生级将输入时钟信号的上升沿转换成脉冲，每个脉冲比期望的占空比短于时钟周期。占空比校正器还包括用于从脉冲时钟信号产生输出时钟信号的脉冲拉伸级，脉冲延伸级以受控的延迟延迟脉冲时钟信号的下降沿。占空比校正器可以包括用于产生作为输出时钟信号的占空比的函数的控制信号的占空比检测器，以及用于将控制信号传送到脉冲拉伸级的反馈路径，以便当占空比小于期望的占空比，并且当占空比大于期望的占空比时减小受控延迟。本发明还涉及一种从输入时钟信号产生具有期望占空比的输出时钟信号的方法。

8. 发明授权

US09842066B2 Integrated circuit comprising an IO buffer driver and method therefor 有权
公开(公告)号：US09842066B2
公开(公告)日：2017-12-12
申请号：US14398876
申请日：2012-05-31
申请人： Michael Priel , Dan Kuzmin , Sergey Sofer
发明人： Michael Priel , Dan Kuzmin , Sergey Sofer
IPC分类号： G06F13/10 , G11C7/04 , G11C7/10 , G06F1/14
CPC分类号： G06F13/10 , G06F1/14 , G11C7/04 , G11C7/106 , G11C7/1069 , G11C7/1087 , G11C7/1096
摘要： An integrated circuit for bias stress condition removal comprising at least one input/output (IO) buffer driver circuit comprising at least one input signal is described. A primary buffer driver stage receives the at least one input signal and providing an output signal in a first time period; and a secondary buffer driver stage receives the at least one input signal and providing an output signal in a second time period. The primary buffer driver stage and the secondary buffer driver stage cooperate and an operational mode of the primary buffer driver stage and an operational mode of the secondary buffer driver stage is varied to produce a varying output signal.

9. 发明授权

US09607117B2 Method and apparatus for calculating delay timing values for an integrated circuit design 有权
公开(公告)号：US09607117B2
公开(公告)日：2017-03-28
申请号：US14650319
申请日：2013-01-08
申请人： Asher Berkovitz , Michael Priel , Sergey Sofer
发明人： Asher Berkovitz , Michael Priel , Sergey Sofer
IPC分类号： G06F17/50 , H03K3/037
CPC分类号： G06F17/5031 , G06F17/5059 , G06F17/5081 , G06F2217/84 , H03K3/0375
摘要： A method of calculating at least one delay timing value for at least one setup timing stage within an integrated circuit design includes applying Negative/Positive Bias Temperature Instability (N/PBTI) compensation margins to delay values for elements within the at least one setup timing stage, and calculating the at least one delay timing value for the at least one setup timing stage based at least partly on the N/PBTI compensation margins applied to the delay values. The method further includes identifying at least partially equivalent elements within the parallel timing paths of the at least one setup timing stage, and applying reduced N/PBTI compensation margins to delay values for the identified at least partially equivalent elements within parallel timing paths of the at least one setup timing stage.

10. 发明授权

US09263433B2 Integrated circuit, integrated circuit package and method of providing protection against an electrostatic discharge event 有权
标题翻译：集成电路，集成电路封装和防静电放电事件的保护方法
公开(公告)号：US09263433B2
公开(公告)日：2016-02-16
申请号：US14359695
申请日：2011-11-22
申请人： Sergey Sofer , Valery Neiman , Michael Priel
发明人： Sergey Sofer , Valery Neiman , Michael Priel
IPC分类号： H02H3/22 , H01L27/02 , H01L23/04 , H01L23/50 , H02H9/04 , H05K1/02
CPC分类号： H01L27/0285 , H01L23/04 , H01L23/50 , H01L2924/0002 , H02H9/04 , H02H9/046 , H05K1/0259 , H01L2924/00
摘要： An integrated circuit comprising a power supply node, a ground node and a gated domain coupled between the power node and the ground node. A Charged Device Model electrostatic discharge protection module is provided for shunting electrical energy of a CDM ESD event away from the gated domain. A gating switch makes an electrical connection in a connected state between the gated domain and at least one of the power node and the ground node. ESD gating control circuitry is coupled to the CDM ESD protection module and controls shunting of energy away from the gated domain by the CDM ESD protection module, thereby avoiding the energy flowing through the gated domain. The ESD gating control circuitry inhibits actuation of the CDM ESD protection module to prevent response to CDM ESD events when the gating domain is powered-up.
摘要翻译：一种集成电路，包括电源节点，接地节点和耦合在功率节点和接地节点之间的选通域。带电装置型号的静电放电保护模块用于将CDM ESD事件的电能与门控域分开。选通开关在门控域与功率节点和接地节点中的至少一个之间的连接状态下进行电连接。 ESD选通控制电路耦合到CDM ESD保护模块，并通过CDM ESD保护模块控制远离门控域的能量分流，从而避免流过门控域的能量。 ESD选通控制电路禁止CDM ESD保护模块的启动，以防止在门控域加电时对CDM ESD事件的响应。

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