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1. 发明申请

US20050117663A1 Chip set for digital audio satellite radio receivers 审中-公开
标题翻译：数字音频卫星无线电接收机芯片组
公开(公告)号：US20050117663A1
公开(公告)日：2005-06-02
申请号：US10933647
申请日：2004-09-03
申请人： Serge Drogi , Mihai Murgulescu , Hans Dropmann
发明人： Serge Drogi , Mihai Murgulescu , Hans Dropmann
IPC分类号： H04B1/18 , H04B1/40 , H04B15/00 , H04L27/00
CPC分类号： H04B1/18 , H04B1/40 , H04L27/00
摘要： A digital audio radio system includes a radio frequency (RF) integrated circuit (IC) and a baseband digital signal processing (DSP) IC to receive digital audio radio signals from satellites and terrestrial antennae. A serial digital interface couples data between the RF IC and the baseband DSP IC to provide a high data rate and low noise. In one embodiment, the RF IC has a single bit sigma delta modulator to convert an analog signal into a serial digital bit stream, and a low voltage differential output driver to reduce the output voltage swing of the serial digital bit stream. The DSP IC has a low voltage differential input receiver to increase the output voltage swing of the serial digital bit stream in the DSP IC, a decimator to lower the data rate of the serial digital bit stream, and a demodulator to convert the serial digital bit stream into parallel digital data samples for digital signal processing by the DSP IC.
摘要翻译：数字音频无线电系统包括射频（RF）集成电路（IC）和基带数字信号处理（DSP）IC，以从卫星和地面天线接收数字音频无线电信号。串行数字接口在RF IC和基带DSP IC之间耦合数据，以提供高数据速率和低噪声。在一个实施例中，RF IC具有单个比特Σ-Δ调制器，以将模拟信号转换成串行数字比特流，以及低电压差分输出驱动器，以减小串行数字比特流的输出电压摆幅。 DSP IC具有低电压差分输入接收器，以增加DSP IC中串行数字位流的输出电压摆幅，降低串行数字位流的数据速率的抽取器，以及用于将串行数字位转换的解调器流入并行数字数据采样，由DSP IC进行数字信号处理。

2. 发明申请

US20050118977A1 Method, apparatus, and systems for digital radio communication systems 审中-公开
标题翻译：用于数字无线电通信系统的方法，装置和系统
公开(公告)号：US20050118977A1
公开(公告)日：2005-06-02
申请号：US10727230
申请日：2003-12-02
申请人： Serge Drogi , Hans Dropmann , Vikas Vinayak
发明人： Serge Drogi , Hans Dropmann , Vikas Vinayak
IPC分类号： H04B1/40 , H04B1/26
CPC分类号： H04B1/0003 , H04B1/40
摘要： A radio system includes a radio frequency (RF) integrated circuit (IC) and a baseband digital signal processing (DSP) IC. A serial digital interface couples data between the RF IC and the DSP IC to provide a high data rate and low noise. In one embodiment, the RF IC has a single bit sigma delta modulator to convert an analog signal into a serial digital bit stream, and a differential output driver to drive the serial digital bit stream as a differential data signal. In one embodiment, the DSP IC has a differential input receiver to receive the differential data signal and generate the serial digital bit stream therein, a decimator to lower the data rate of the serial digital bit stream and convert it into parallel digital data samples, and a demodulator to digitally demodulate the parallel digital data samples into data words for digital signal processing.
摘要翻译：无线电系统包括射频（RF）集成电路（IC）和基带数字信号处理（DSP）IC。串行数字接口在RF IC和DSP IC之间耦合数据，以提供高数据速率和低噪声。在一个实施例中，RF IC具有单个比特Σ-Δ调制器以将模拟信号转换为串行数字位流，以及差分输出驱动器，以将串行数字位流驱动为差分数据信号。在一个实施例中，DSP IC具有差分输入接收器，用于接收差分数据信号并在其中产生串行数字位流，抽取器降低串行数字位流的数据速率并将其转换为并行数字数据采样，以及解调器，用于将并行数字数据样本数字解调为用于数字信号处理的数据字。

3. 发明申请

US20060128347A1 Radio integrated circuit with integrated power amplifier 审中-公开
标题翻译：无线电集成电路与集成功率放大器
公开(公告)号：US20060128347A1
公开(公告)日：2006-06-15
申请号：US11353639
申请日：2006-02-13
申请人： Pramote Piriyapoksombut , Gordon Olsen , Joel King , Serge Drogi , Hans Dropmann , Vikas Vinayak
发明人： Pramote Piriyapoksombut , Gordon Olsen , Joel King , Serge Drogi , Hans Dropmann , Vikas Vinayak
IPC分类号： H04B1/28
CPC分类号： H04B1/0003 , H04B1/40
摘要： A radio system includes a radio frequency (RF) integrated circuit (IC), a baseband digital signal processing (DSP) IC, and a serial digital interface coupling data there-between. In one embodiment of the invention, the RF IC has an input receiver to receive a serial digital transmission bit stream from a digital signal processing integrated circuit; a data recoverer coupled to the input receiver to recover digital data bits from the serial digital transmission bit stream; a low pass filter coupled to the data recoverer convert the digital data bits into an analog transmission signal; a mixer coupled to the low pass filter to up-convert the analog transmission signal from a baseband frequency to a second selectable carrier frequency as a transmit radio frequency signal; and an amplifier coupled to the mixer and an antenna, the amplifier to amplify the transmit radio frequency signal for broadcast over the antenna.
摘要翻译：无线电系统包括射频（RF）集成电路（IC），基带数字信号处理（DSP）IC以及耦合数据的串行数字接口。在本发明的一个实施例中，RF IC具有用于从数字信号处理集成电路接收串行数字传输比特流的输入接收器; 耦合到输入接收器的数据恢复器，用于从串行数字传输比特流中恢复数字数据位; 耦合到数据的低通滤波器将数字数据位转换成模拟传输信号; 耦合到低通滤波器的混频器，用于将模拟传输信号从基带频率上升转换为第二可选载波频率作为发射射频信号; 以及耦合到所述混频器和天线的放大器，所述放大器放大所述发射射频信号以在所述天线上广播。

4. 发明申请

US20050119025A1 Serial digital interface for wireless network radios and baseband integrated circuits 审中-公开
标题翻译：无线网络无线电和基带集成电路的串行数字接口
公开(公告)号：US20050119025A1
公开(公告)日：2005-06-02
申请号：US10988362
申请日：2004-11-12
申请人： Rishi Mohindra , Serge Drogi , Hans Dropmann , Vikas Vinayak
发明人： Rishi Mohindra , Serge Drogi , Hans Dropmann , Vikas Vinayak
IPC分类号： H04B1/40 , H04B1/44 , H04M1/00
CPC分类号： H04B1/0021
摘要： A wireless radio for wireless networking communication systems includes a radio frequency (RF) transceiver integrated circuit (IC) and a baseband digital signal processing (DSP) IC. A bidirectional serial digital interface couples data between the RF transceiver IC and the DSP IC to provide a high data rate and low noise. The bidirectional serial digital interface includes a first serial data connection and a second serial data connection. In one embodiment, the RF transceiver IC has a single bit sigma delta A/D modulator to convert an analog signal into a first serial digital bit stream for communication over the first serial data connection. In one embodiment, the DSP IC has a single bit sigma delta digital modulator to generate a second serial digital bit stream for communication over the second serial data connection.
摘要翻译：用于无线网络通信系统的无线电无线电包括射频（RF）收发器集成电路（IC）和基带数字信号处理（DSP）IC。双向串行数字接口在RF收发器IC和DSP IC之间耦合数据，以提供高数据速率和低噪声。双向串行数字接口包括第一串行数据连接和第二串行数据连接。在一个实施例中，RF收发器IC具有单个比特Σ-ΔA/ D调制器，以将模拟信号转换为第一串行数字比特流，以在第一串行数据连接上进行通信。在一个实施例中，DSP IC具有单个位Σ-Δ数字调制器，以产生用于通过第二串行数据连接进行通信的第二串行数字位流。

5. 发明申请

US20070218848A1 PHASE ERROR DE-GLITCHING CIRCUIT AND METHOD OF OPERATING 有权
标题翻译：相位误差去除电路和操作方法
公开(公告)号：US20070218848A1
公开(公告)日：2007-09-20
申请号：US11671423
申请日：2007-02-05
申请人： Serge Drogi , Vikas Vinayak , Mark Gehring , Martin Tomasz
发明人： Serge Drogi , Vikas Vinayak , Mark Gehring , Martin Tomasz
IPC分类号： H04B1/04 , H01Q11/12
CPC分类号： H03F1/0205 , H03F1/0227 , H03F1/0238 , H03F1/3247 , H03F2200/451 , H03F2200/78 , H03F2200/99 , H03G3/004 , H03G3/3042
摘要： A system including a phase comparator to compare a first signal and a second signal to generate a phase error signal, and a controller to generate an adjusted phase error signal from the phase error signal in response to an amplitude of at least one of the first signal and the second signal.
摘要翻译：一种系统，包括相位比较器，用于比较第一信号和第二信号以产生相位误差信号;以及控制器，响应于所述第一信号中的至少一个的振幅，从所述相位误差信号产生经调整的相位误差信号和第二个信号。

6. 发明申请

US20070184796A1 AMPLIFIER COMPRESSION CONTROLLER CIRCUIT 有权
标题翻译：放大器压缩控制器电路
公开(公告)号：US20070184796A1
公开(公告)日：2007-08-09
申请号：US11670931
申请日：2007-02-02
申请人： Serge Drogi , Vikas Vinayak
发明人： Serge Drogi , Vikas Vinayak
IPC分类号： H04B1/04 , H01Q11/12
CPC分类号： H03F1/0205 , H03F1/0227 , H03F1/0238 , H03F1/3247 , H03F2200/451 , H03F2200/78 , H03F2200/99 , H03G3/004 , H03G3/3042
摘要： A power amplifier controller circuit controls a power amplifier based upon an amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The power amplifier controller circuit comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal. The amplitude loop may include a variable gain amplifier adjusting the amplitude of the input signal. The amplitude loop can include a compression control block which may be configured either to adjust the gain in the variable gain amplifier or the voltage from the power supply based upon the operating level of the other, in addition to being based upon the amplitude correction signal, thus providing a way of maintaining the depth beyond the PA's compression point and allowing a control of the efficiency of the RF power amplifier.
摘要翻译：功率放大器控制器电路基于指示输入信号的幅度与输出信号的衰减幅度之间的幅度差的振幅校正信号来控制功率放大器。功率放大器控制器电路包括幅度控制回路和相位控制回路。幅度控制环路根据振幅校正信号调整功率放大器的电源电压。振幅环路可以包括调整输入信号的幅度的可变增益放大器。振幅回路可以包括压缩控制块，除了基于幅度校正信号之外，压缩控制块可被配置为基于另一个的操作电平来调整可变增益放大器中的增益或来自电源的电压，从而提供了保持深度超过PA压缩点的方式，并允许控制RF功率放大器的效率。

7. 发明申请

US20070184795A1 AMPLITUDE ERROR DE-GLITCHING CIRCUIT AND METHOD OF OPERATING 有权
标题翻译：放大器错误去除电路和操作方法
公开(公告)号：US20070184795A1
公开(公告)日：2007-08-09
申请号：US11670402
申请日：2007-02-01
申请人： Serge Drogi , Vikas Vinayak , Martin Tomasz
发明人： Serge Drogi , Vikas Vinayak , Martin Tomasz
IPC分类号： H04B1/04 , H01Q11/12
CPC分类号： H03F1/0205 , H03F1/0227 , H03F1/0238 , H03F1/3247 , H03F3/24 , H03F2200/451 , H03F2200/78 , H03F2200/99 , H03G3/004 , H03G3/3042 , H04B1/0475 , H04B2001/0408
摘要： A power amplifier controller circuit controls a power amplifier based upon an amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The power amplifier controller circuit comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal. The RF power amplifier system may reduce the corrective action of the amplitude loop during periods of relatively rapid changes in amplitude, and thus distortion can be further reduced.
摘要翻译：功率放大器控制器电路基于指示输入信号的幅度与输出信号的衰减幅度之间的幅度差的振幅校正信号来控制功率放大器。功率放大器控制器电路包括幅度控制回路和相位控制回路。幅度控制环路根据振幅校正信号调整功率放大器的电源电压。 RF功率放大器系统可以在幅度相对快速变化的时段期间减小幅度回路的校正动作，从而可以进一步减小失真。

8. 发明申请

US20070184791A1 Power amplifier controller circuit 有权
标题翻译：功率放大器控制器电路
公开(公告)号：US20070184791A1
公开(公告)日：2007-08-09
申请号：US11429119
申请日：2006-05-04
申请人： Vikas Vinayak , Serge Drogi
发明人： Vikas Vinayak , Serge Drogi
IPC分类号： H01Q11/12
CPC分类号： H03G3/3042 , H03F1/0205 , H03F1/0227 , H03F1/0238 , H03F1/3247 , H03F2200/451 , H03F2200/78 , H03F2200/99 , H03G3/004
摘要： A power amplifier controller circuit controls a power amplifier based upon an amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The power amplifier controller circuit comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal. The amplitude correction signal may also be split into two or more signals with different frequency ranges and provided respectively to different types of power supplies with different efficiencies to generate the adjusted supply voltage to the power amplifier. The phase control loop adjusts the phase of the input signal based upon a phase error signal indicating a phase difference between phases of the input signal and the output signal to reduce phase distortion generated by the power amplifier.
摘要翻译：功率放大器控制器电路基于指示输入信号的幅度与输出信号的衰减幅度之间的幅度差的振幅校正信号来控制功率放大器。功率放大器控制器电路包括幅度控制回路和相位控制回路。幅度控制环路根据振幅校正信号调整功率放大器的电源电压。幅度校正信号也可以被分成具有不同频率范围的两个或更多个信号，并分别提供给具有不同效率的不同类型的电源，以产生对功率放大器的调整的电源电压。相位控制环路基于表示输入信号的相位与输出信号的相位差的相位误差信号来调整输入信号的相位，以减小由功率放大器产生的相位失真。

9. 发明申请

US20070184794A1 RF Power Amplifier Controller Circuit Including Calibrated Phase Control Loop 有权
标题翻译：包括校准相位控制回路的RF功率放大器控制器电路
公开(公告)号：US20070184794A1
公开(公告)日：2007-08-09
申请号：US11669648
申请日：2007-01-31
申请人： Serge Drogi , Vikas Vinayak , Mark Gehring , Cary Renzema , Jeremy Lubkin
发明人： Serge Drogi , Vikas Vinayak , Mark Gehring , Cary Renzema , Jeremy Lubkin
IPC分类号： H04B1/04 , H01Q11/12
CPC分类号： H03F1/0205 , H03F1/0227 , H03F1/0238 , H03F1/3247 , H03F3/24 , H03F2200/451 , H03F2200/78 , H03F2200/99 , H03G3/004 , H03G3/3042 , H04B2001/0408
摘要： An RF power amplifier system comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The phase control loop adjusts the phase of the input signal based upon a phase error signal indicating a phase difference between phases of the input signal and the output signal. The phase control loop may comprise one or more variable phase delays introducing a relative phase delay to allow the phase differences between the input and output signals of the PA circuit to be within a range compatible with a phase comparator generating the phase error signal, and a low frequency blocking module that removes the larger extent, lower frequency components of the phase error signal.
摘要翻译： RF功率放大器系统包括幅度控制环路和相位控制环路。幅度控制环路基于表示输入信号的振幅与输出信号的衰减幅度之间的振幅差的振幅校正信号，调整功率放大器的电源电压。相位控制环路基于表示输入信号的相位与输出信号的相位差的相位误差信号来调整输入信号的相位。相位控制回路可以包括引入相对相位延迟的一个或多个可变相位延迟，以允许PA电路的输入和输出信号之间的相位差在与产生相位误差信号的相位比较器兼容的范围内，以及低频阻塞模块可以消除较大的程度，降低频率分量的相位误差信号。

10. 发明授权

US06490440B1 Digital transmitter circuit and method of operation 失效
标题翻译：数字发射机电路及操作方法
公开(公告)号：US06490440B1
公开(公告)日：2002-12-03
申请号：US09323236
申请日：1999-06-01
申请人： James S. Mielke , Albert H. Higashi , Serge Drogi
发明人： James S. Mielke , Albert H. Higashi , Serge Drogi
IPC分类号： H04B102
CPC分类号： H04B1/0483 , H04B1/406
摘要： A transceiver (10) includes a transmitter (16) that receives a digital data stream from a digital signal processor (18) to delay lines (20, 30). The delay lines (20, 30) provide an address to a ROM look-up table (40). Another input of the look-up table (40) receives a signal that selects protocols such as TDMA, CDMA, and GSM. A multi-accumulator fractional-N synthesizer (48) receives phase derivative coefficients and a DAC (46) receives amplitude modulation coefficients from the look-up table (40) based on the selected protocol. The analog output signals from the DAC (46) and the synthesizer (48) are received by a variable gain amplifier (54) that generates an RF amplitude and frequency modulated output signal for transmission from the transmitter (16).
摘要翻译：收发器（10）包括从数字信号处理器（18）接收数字数据流以延迟线（20,30）的发射器（16）。延迟线（20,30）向ROM查找表（40）提供地址。查找表（40）的另一个输入接收选择诸如TDMA，CDMA和GSM之类的协议的信号。多累加器分数N合成器（48）接收相位导数系数，并且DAC（46）基于所选择的协议从查找表（40）接收幅度调制系数。来自DAC（46）和合成器（48）的模拟输出信号被可变增益放大器（54）接收，该可变增益放大器产生用于从发送器（16）传输的RF幅度和调频输出信号。

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